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TAS5352ADDV Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5352ADDV Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 27 page  ELECTRICAL CHARACTERISTICS TAS5352A SLES239 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 25°C, fS = 384 kHz, unless otherwise specified. TAS5352A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX Internal Voltage Regulator and Current Consumption Voltage regulator, only used as a VREG VDD = 12 V 3 3.3 3.6 V reference node Operating, 50% duty cycle 7.2 17 IVDD VDD supply current mA Idle, reset mode 5.5 11 50% duty cycle 8 16 IGVDD_X Gate supply current per half-bridge mA Reset mode 1 1.8 50% duty cycle, with 10 µH and 470 nF output 19.0 25 mA filter. IPVDD_X Half-bridge idle current Reset mode, no switching 525 630 µA Output Stage MOSFETs Drain-to-source resistance, Low RDSon,LS TJ = 25°C, excludes metalization resistance, 80 89 m Ω Side Drain-to-source resistance, High RDSon,HS TJ = 25°C, excludes metalization resistance, 80 89 m Ω Side I/O Protection Undervoltage protection limit, Vuvp,G 9.5 V GVDD_X Vuvp,hyst (1) Undervoltage protection limit, 250 mV GVDD_X BSTuvpF Puts device into RESET when BST 5.9 V voltage falls below limit BSTuvpR Brings device out of RESET when 7 V BST voltage rises above limit OTW(1) Overtemperature warning 115 125 135 °C Temperature drop needed below OTWHYST (1) OTW temp. for OTW to be inactive 25 °C after the OTW event OTE(1) Overtemperature error threshold 145 155 165 °C OTE- OTE - OTW differential, temperature 30 °C OTWdifferential (1) delta between OTW and OTE OLPC Overload protection counter fS = 384 kHz 1.25 ms Resistor—programmable, high-end, IOC Overcurrent limit protection 10.9 A ROC = 22 kΩ with 1 mS pulse IOCT Overcurrent response time 150 ns tACTIVITY Time for PWM activity detector to Lack of transition of any PWM input 13.2 µS DETECTOR activate when no PWM is present Connected when RESET is active to provide Output pulldown current of each IPD bootstrap capacitor charge. Not used in SE 3 mA half-bridge mode. Static Digital Specifications VIH High-level input voltage 2 V PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD VIL Low-level input voltage 0.8 V ILeakage Input leakage current 100 µA OTW/SHUTDOWN (SD) Internal pullup resistance, OTW to RINT_PU 20 26 32 k Ω VREG, SD to VREG Internal pullup resistor 3 3.3 3.6 VOH High-level output voltage V External pullup of 4.7 k Ω to 5 V 4.5 5 (1) Specified by design 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS5352A |
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