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TAS5424B-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS5424B-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 46 page SCL SDA t w(H) t w(L) t r t f t su1 t h1 T0027-01 SCL SDA t h2 t (buf) t su2 t su3 Start Condition Stop Condition T0028-01 TAS5414B-Q1 TAS5424B-Q1 www.ti.com SLOS673 – DECEMBER 2011 TIMING REQUIREMENTS FOR I 2C INTERFACE SIGNALS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tr Rise time for both SDA and SCL signals 300 ns tf Fall time for both SDA and SCL signals 300 ns tw(H) SCL pulse duration, high 0.6 μs tw(L) SCL pulse duration, low 1.3 μs tsu2 Setup time for START condition 0.6 μs th2 START condition hold time after which first clock pulse is generated 0.6 μs tsu1 Data setup time 100 ns th1 Data hold time 0(1) ns tsu3 Setup time for STOP condition 0.6 μs CB Load capacitance for each bus line 400 pF (1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. Figure 1. SCL and SDA Timing Figure 2. Timing for Start and Stop Conditions Copyright © 2011, Texas Instruments Incorporated 11 |
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