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IDT82V3011 Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT82V3011 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 30 page  10 IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE The mode changes between Normal (S1) and Auto-Holdover (S2) are triggered by the Invalid Input Reference Detection Circuit and are irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At the stage of S1, if the input reference is invalid (out of the capture range), the operating mode will be changed to Auto-Holdover (S2) automatically. When the input reference becomes valid, the operating mode will be changed back to Normal (S1) automatically. Refer to “2.4 Invalid Input Signal Detection” for more information. When changing the operating mode, the TIE control block is enabled/ disabled automatically by the state control circuit as shown in Figure - 3, except for the changes from Normal (S1) to Auto-Holdover (S2), and from Auto-Holdover (S2) and Holdover (S3) to Normal (S1). During these three changes, the TIE control block can be enabled or disabled, depending on the logic level on the TIE_en pin. 2.1.1 NORMAL MODE The Normal mode is typically used when a slave clock source synchronized to the network is required. In this mode, the IDT82V3011 provides timing (C1.5o, C3o, C2o, C4o, C8o, C16o, C19o, C32o) and synchronization (F0o, F8o, F16o, F19o, F32o, TSP, RSP) signals. All these signals are synchronous to the input reference. The nominal frequency of the input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. After reset, the IDT82V3011 will take 30 seconds at most to make the output signals synchronous (phase locked) to the input reference. Whenever the IDT82V3011 works in the Normal mode, the NORMAL pin will be set to logic high. 2.1.2 FAST LOCK MODE The Fast Lock mode is a submode of the Normal mode. It allows the DPLL to lock to a reference more quickly than the Normal mode allows. Typically, the locking time in the Fast Lock mode is less than 500 ms. When the FLOCK pin is set to high, the Fast Lock mode will be enabled. 2.1.3 HOLDOVER MODE The Holdover mode is typically used for short duration (e.g., 2 seconds) while network synchronization is temporarily disrupted. In the Holdover mode, the IDT82V3011 provides timing and synchronization signals that are not locked to an external reference signal, but are based on storage techniques. In the Normal mode, when the output frequency is locked to the input reference signal, a numerical value corresponding to the output frequency is stored alternately in two memory locations every 30 ms. When the device is changed to the Holdover mode, the stored value from between 30 ms and 60 ms is used to set the output frequency of the device. The frequency accuracy in the Holdover mode is ±0.025 ppm, which corresponds to a worst case of 18 frame (125 µs per frame) slips in 24 hours. This meets the AT&T TR62411 requirement of ±0.37 ppm (255 frame slips per 24 hours). Whenever the IDT82V3011 works in the Holdover mode, the HOLDOVER pin will be set to logic high. 2.1.4 FREERUN MODE The Freerun mode is typically used when a master clock source is required, or used when a system is just powered up and the network synchronization has not been achieved. In this mode, the IDT82V3011 provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the input reference signal. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32 ppm output clock is required, the master clock must also be ±32 ppm. Refer to “2.7 OSC” for more information. Whenever the IDT82V3011 works in the Freerun mode, the FREERUN pin will be set to logic high. 2.2 FREQUENCY SELECT CIRCUIT The input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz, as determined by the F_sel1 and F_sel0 pins. See Table - 2 for details. Every time the frequency is changed, the device must be reset to make the change effective. 2.3 REFERENCE INPUT MONITOR The Telcordia GR-1244-CORE standard recommends that the DPLL should be able to reject the references that are off the nominal frequency by more than ±12 ppm. The IDT82V3011 monitors the frequency of the input reference and outputs a signal at MON_out pin to indicate the monitoring result. Whenever the reference frequency is off the nominal frequency by more than ±12 ppm, the MON_out pin will go high. The signal at MON_out pin is updated every 2 seconds. 2.4 INVALID INPUT SIGNAL DETECTION This circuit is used to detect if the input reference is out of the capture range. Refer to “3.6 Capture Range” for details. This includes a complete loss of the input reference and a large frequency shift in the input reference. If the input reference is invalid (out of the capture range), the IDT82V3011 will be automatically changed to the Holdover mode (Auto- Holdover). When the input reference becomes valid, the device will be changed back to the Normal mode and the output signals will be locked to the input reference. In the Holdover mode, the output signals are based on the output reference signal 30 ms to 60 ms prior to entering the Holdover mode. The amount of phase drift while in holdover can be negligible because the Holdover mode is very accurate (e.g., 0.025 ppm). Consequently, the phase delay between the input and output after switching back to the Normal mode is preserved. Table - 2 Input Frequency Selection Frequency Selection Pins Input Frequency F_sel1 F_sel0 0 0 19.44 MHz 01 8 kHz 1 0 1.544 MHz 1 1 2.048 MHz |
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