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TDC7201ZAXT Datasheet(PDF) 6 Page - Texas Instruments |
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TDC7201ZAXT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 50 page 6 TDC7201 SNAS686 – MAY 2016 www.ti.com Product Folder Links: TDC7201 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Accuracy is defined as the systematic error in the output signal; the error of the device excluding noise. (2) Specified by design. (3) Sum of TDC1 and TDC2 values 6.5 Electrical Characteristics TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TDC CHARACTERISTICS LSB Resolution Single shot measurement 55 ps TACC-2 Accuracy (Mode 2)(1) CLOCK = 8 MHz, Jitter (RMS) < 1 ps, Stability < 5 ppm 28 ps TSTD-2 Standard Deviation (Mode 2) Measured time = 100 µs 50 ps Measured time = 1 µs 35 ps OUTPUT CHARACTERISTICS: TRIGG1, TRIGG2, INTB1, INTB2, DOUT1, DOUT2 VOH Output voltage high Isource = –2 mA 2.31 2.95 V VOL Output voltage low Isink = 2 mA 0.35 0.99 V INPUT CHARACTERISTICS: START1, STOP1, START2, STOP2, CSB1, CSB2 Cin Input capacitance(2) 4 pF INPUT CHARACTERISTICS: ENABLE, CLOCK, DIN, SCLK Cin Input capacitance(2) 8 pF POWER CONSUMPTION(3) (see Measurement Mode 1 and Measurement Mode 2) Ish Shutdown current EN = LOW 0.6 µA IQA Quiescent Current A EN = HIGH; TDC running 2.7 mA IQB Quiescent Current B EN = HIGH; TDC OFF, Clock Counter running 140 µA IQC Quiescent Current C EN = HIGH; measurement stopped, SPI communication only 175 µA IQD Quiescent Current D EN = HIGH, TDC OFF, counter stopped, no communication 100 µA 6.6 Timing Requirements MIN NOM MAX UNIT TIMING REQUIREMENTS: START1, STOP1, START2, STOP2, CLOCK PWSTART Pulse width for Start Signal 10 ns PWSTOP Pulse width for Stop Signal 10 ns SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 25 MHz) (See Figure 1) fSCLK SCLK frequency 25 MHz t1 SCLK period 40 ns SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 20 MHz) (See Figure 1) t1 SCLK period 50 ns t2 SCLK High Time 16 ns t3 SCLK Low Time 16 ns t4 DIN setup time 5 ns t5 DIN hold time 5 ns t6 CSB1 or CSB2 fall to SCLK rise 6 ns t7 Last SCLK rising edge to CSB1 or CSB2 rising edge 6 ns t8 Minimum pause time (CSB high) 40 ns t9 Clk fall to DOUT1 or DOUT2 bus transition 12 ns |
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