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TFP401, TFP401A

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SLDS120G – MARCH 2000 – REVISED MAY 2016

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Copyright © 2000–2016, Texas Instruments Incorporated

Pin Functions (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

QO[8:15]

59–66

DO

Odd green-pixel output – Output for odd-only green pixel when in 2-pixel/clock mode. Not

used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output

data clock, ODCK.

LSB: QO8/pin 59

MSB: QO15/pin 66

QO[16:23]

69–75, 77

DO

Odd red-pixel output – Output for odd-only red pixel when in 2-pixel/clock mode. Not used,

and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data

clock, ODCK.

LSB: QO16/pin 69

MSB: QO23/pin 77

QE[0:7]

10–17

DO

Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode.

Output for even-only blue pixel when in 2-pixel per clock mode. Output data is synchronized

to the output data clock, ODCK.

LSB: QE0/pin 10

MSB: QE7/pin 17

RxC+

93

AI

Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal

differential input pair

RxC–

94

AI

Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal

differential input pair

Rx0+

90

AI

Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal

differential input pair.

Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in

blank.

Rx0–

91

AI

Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal

differential input pair

Rx1+

85

AI

Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal

differential input pair

Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.

Rx1–

86

AI

Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal

differential input pair

Rx2+

80

AI

Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal

differential input pair

Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank.

Rx2–

81

AI

Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal

differential input pair

SCDT

8

DO

Sync detect - Output to signal when the link is active or inactive. The link is considered to be

active when DE is actively switching. The TFP401/401A monitors the state of DE to

determine link activity. SCDT can be tied externally to PDO to power down the output drivers

when the link is inactive.

High: Active link

Low: Inactive link

ST

3

DI

Output drive strength select – Selects output drive strength for high- or low-current drive.

High: High drive strength

Low: Low drive strength

STAG

7

DI

Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS =

high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal

operation outputs the odd and even pixels simultaneously.

High: Normal simultaneous even/odd pixel output

Low: Time-staggered even/odd pixel output

VSYNC

47

DO

Vertical sync output