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THS1041IPWR Datasheet(PDF) 7 Page - Texas Instruments |
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THS1041IPWR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 42 page THS1041 SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004 7 www.ti.com electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued) digital specifications PARAMETER MIN NOM MAX UNIT Digital Inputs VIH High-level input voltage Clock input 0.8 × AVDD V VIH High-level input voltage All other inputs 0.8 × DVDD V VIL Low-level input voltage Clock input 0.2 × AVDD V VIL Low-level input voltage All other inputs 0.2 × DVDD V IIH High-level input current 1 µA IIL Low-level input current |−1| µA Ci Input capacitance 5 pF Digital Outputs VOH High-level output voltage Iload = 50 µA DVDD−0.4 V VOL Low-level output voltage Iload = 50 µA 0.4 V High impedance output current ±1 µA Rise/fall time Cload = 15 pF 3.5 ns Clock Input tc Clock cycle 25 200 ns tw(CKH) Pulse duration, clock high 11.25 110 ns tw(CKL) Pulse duration, clock low 11.25 110 ns Clock duty cycle 45% 50% 55% td(o) Clock to data valid, delay time 9.5 16 ns Pipeline latency 4 Cycles td(AP) Aperture delay time 0.1 ns Aperture uncertainty (jitter) 1 ps timing PARAMETER MIN TYP MAX UNIT td(DZ) Output disable to Hi-Z output, delay time 0 10 ns td(DEN) Output enable to output valid, delay time 0 10 ns td(OEW) Output disable to write enable, delay time 12 ns td(WOE) Write disable to output enable, delay time 12 ns tw(WP) Write pulse duration 15 ns tsu Input data setup time 5 ns th Input data hold time 5 ns |
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