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THS5651AIDWRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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THS5651AIDWRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 33 page THS5651A 10BIT, 125 MSPS, CommsDAC DIGITALTOANALOG CONVERTER SLAS260A − FEBRUARY 2000 − REVISED SEPTEMBER 2002 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load (unless otherwise noted) ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog output fCLK Maximum output update rate DVDD = 4.5 V to 5.5 V 100 125 MSPS fCLK Maximum output update rate DVDD = 3 V to 3.6 V 70 100 MSPS ts(DAC) Output settling time to 0.1%† 35 ns tpd Output propagation delay 1 ns GE Glitch energy‡ Worst case LSB transition (code 511 − code 512) 5 pV−s tr(IOUT) Output rise time 10% to 90%† 1 ns tf(IOUT) Output fall time 90% to 10%† 1 ns Output noise IOUTFS = 20 mA 15 pA/ √HZ Output noise IOUTFS = 2 mA 10 pA/ √HZ AC linearity§ fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C −72 THD Total harmonic distortion fCLK = 50 MSPS, fOUT = 1 MHz, TA = −40°C to 85°C −72 −64 dBc THD Total harmonic distortion fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25°C −70 dBc fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25°C −70 fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C 79 fCLK = 50 MSPS, fOUT= 1 MHz, TA = −40°C to 85°C 66 fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C 77 Spurious free dynamic range to fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25°C 75 Spurious free dynamic range to Nyquist fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25°C 71 dBc SFDR Nyquist fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25°C 58 dBc SFDR fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25°C 69 fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25°C 61 fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25°C 62 Spurious free dynamic range fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25°C,1 MHz span 82 Spurious free dynamic range within a window fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span 81 dBc within a window fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span 78 dBc † Measured single ended into 50 Ω load at IOUT1. ‡ Single-ended output IOUT1, 50 Ω doubly terminated load. § Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range from 45%/55% to 55%/45%. |
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