THS12082

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS271B – MAY 2000 – REVISED DECEMBER 2002

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AINP

30

I

Analog input, single-ended or positive input of differential channel A

AINM

29

I

Analog input, single-ended or negative input of differential channel A

AVDD

23

I

Analog supply voltage

AGND

24

I

Analog ground

BVDD

7

I

Digital supply voltage for buffer

BGND

8

I

Digital ground for buffer

CONV_CLK

(CONVST)

15

I

Digital input. This input is used to apply an external conversion clock in the continuous conversion mode.

In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low

transition on this input holds simultaneously the selected analog input channels and initiates a single

conversion of all selected analog inputs.

CS0

22

I

Chip select input (active low)

CS1

21

I

Chip select input (active high)

DATA_AV

16

O

Data available signal, which can be used to generate an interrupt for processors and as a level

information of the internal FIFO. This signal can be configured to be active low or high and can be

configured as a static level or pulse output. See Table 14.

DGND

17

I

Digital ground. Ground reference for digital circuitry.

DVDD

18

I

Digital supply voltage

D0 – D9

1–6, 9–12

I/O/Z

Digital input, output; D0 = LSB

RA0/D10

13

I/O/Z

Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This

is required for writing to control register 0 and control register 1. See Table 8.

RA1/D11

14

I/O/Z

Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control

register. This is required for writing to control register 0 and control register 1. See Table 8.

OV_FL

32

O

Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if

an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO.

REFIN

28

I

Common-mode reference input for the analog input channels. It is recommended that this pin be

connected to the reference output REFOUT.

REFP

26

I

Reference input, requires a bypass capacitor of 10

µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed

through control register 0. See Table 9.

REFM

25

I

Reference input, requires a bypass capacitor of 10

µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed

through control register 0. See Table 9.

RESET

31

I

Hardware reset of the THS12082. Sets the control register to default values.

REFOUT

27

O

Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250

µA. The reference

output requires a capacitor of 10

µF to AGND for filtering and stability.

RD†

19

I

The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,

active low as a data read select from the processor. See timing section.

WR (R/W)†

20

I

This input is programmable. It functions as a read-write input (R/W) and can also be configured as a

write-only input (WR), which is active low and used as data write select from the processor. In this case,

the RD input is used as a read input from the processor. See timing section.

† The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.