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THS12082 Datasheet(PDF) 7 Page - Texas Instruments |
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THS12082 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page  THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS SLAS271B – MAY 2000 – REVISED DECEMBER 2002 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing specifications (AVDD = BVDD = DVDD = 5 V, VREFP = 3.5 V, VREFM = 1.5 V, CL < 30 pF )† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA_AV) Delay time 5 ns td(o) Delay time 5 ns td(pipe) Latency 5 CONV CLK † Refer to Figure 2 timing specification of the single conversion mode‡ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tc Clock cycle of the internal clock oscillator 117 125 133 ns t1 Pulse duration CONVST 1 analog input 1.5 ×tc ns t1 Pulse duration, CONVST 2 analog inputs 2.5 ×tc ns tdA Aperture time 1 ns t2 Time between consecutive start of single 1 analog input 2 ×tc ns t2 g conversion 2 analog inputs 3 ×tc ns 1 analog input, TL = 1 6.5 ×tc+15 ns 2 analog inputs, TL = 2 7.5 ×tc+15 ns 1 analog input, TL = 4 3 ×t2 +6.5×tc+15 ns td(DATA AV) Delay time, DATA_AV becomes active for the 2 analog inputs, TL = 4 t2 +7.5×tc+15 ns td(DATA_AV) y, _ trigger level condition: TRIG0 = 1, TRIG1 = 1 1 analog input, TL = 8 7 ×t2 +6.5×tc+15 ns 2 analog inputs, TL = 8 3 ×t2 +7.5×tc+15 ns 1 analog input, TL = 14 13 ×t2 +6.5×tc+15 ns 2 analog inputs, TL = 12 5 ×t2 +7.5×tc+15 ns ‡ Refer to Figure 1 |
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