CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 7 of 13
Switching Characteristics Over the Operating Range[9]
Parameter
Description
7C133-25
7C143-25
7C133-35
7C143-35
7C133-55
7C143-55
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
25
35
55
ns
tAA
Address to Data Valid[10]
25
35
55
ns
tOHA
Data Hold from Address Change
0
0
0
ns
tACE
CE LOW to Data Valid[10]
25
35
55
ns
tDOE
OE LOW to Data Valid[10]
20
25
30
ns
tLZOE
OE LOW to Low Z[11, 12,13]
3
3
3
ns
tHZOE
OE HIGH to High Z[11, 12,13]
15
20
25
ns
tLZCE
CE LOW to Low Z[11, 12,13]
3
5
5
ns
tHZCE
CE HIGH to High Z[11, 12,13]
15
20
20
ns
tPU
CE LOW to Power-Up[13]
0
0
0
ns
tPD
CE HIGH to Power-Down[13]
25
25
25
ns
Write Cycle[14]
tWC
Write Cycle Time
25
35
55
ns
tSCE
CE LOW to Write End
20
25
40
ns
tAW
Address Set-up to Write End
20
25
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
20
25
35
ns
tSD
Data Set-up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
R/W LOW to High Z[12,13]
15
20
20
ns
tLZWE
R/W HIGH to Low Z[12,13]
0
0
0
ns
Busy/Interrupt Timing (for master CY7C133)
tBLA
BUSY Low from Address Match
25
35
50
ns
tBHA
BUSY High from Address Mismatch
20
30
40
ns
tBLC
BUSY Low from CE LOW
20
25
35
ns
tBHC
BUSY High from CE HIGH
20
20
30
ns
tWDD
Write Pulse to Data Delay[15]
50
60
80
ns
tDDD
Write Data Valid to Read Data Valid[15]
35
45
55
ns
tBDD
BUSY High to Valid Data[16]
Note 16
Note 16
Note 16
ns
tPS
Arbitration Priority Set Up Time[17]
5
5
5
ns
Busy Timing (for slave CY7C143)
tWB
Write to BUSY[18]
0
0
0
ns
tWH
Write Hold After BUSY[19]
20
25
30
ns
tWDD
Write Pulse to Data Delay[20]
50
60
80
ns
tDDD
Write Data Valid to Read Data Valid[20]
35
45
55
ns
Notes:
9.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capacitance.
10. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
11. At any given temperature and voltage condition for any given device, tLZCE is less than tHZCE and tLZOE is less than tHZOE.
12. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
13. This parameter is guaranteed but not tested.
14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.”
16. tBDD is a calculated parameter and is greater of 0,tWDD–tWP (actual) or tDDD–tDW (actual).
17. To ensure that the earlier of the two ports wins.
18. To ensure that write cycle is inhibited during contention.
19. To ensure that a write cycle is completed after contention.
20. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with Port-to-port Delay.”
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