DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM

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Table 1. Operating Modes

CE

OE

WE

DQ0–DQ7

MODE

POWER

X

X

High-Z

Deselect

Standby

X

Write

Active

Read

Active

High-Z

Read

Active

X

X

X

High-Z

Deselect

CMOS Standby

X

X

X

High-Z

Data Retention

Battery Current

DATA-READ MODE

The DS1556 is in the read mode whenever

CE (chip enable) is low and WE (write enable) is high. The

device architecture allows ripple-through access to any valid address location. Valid data will be available

satisfied. If

CE or OE access times are not met, valid data will be available at the latter of chip enable

controlled by

access.

DATA-WRITE MODE

The DS1556 is in the write mode whenever

WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of

WE or CE. The addresses must be held valid throughout the

cycle.

a typical application, the

OE signal will be high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus contention. If

OE is low prior to WE

transitioning low, the data bus can become active with read data defined by the address inputs. A low

transition on

DATA-RETENTION MODE

levels.

nominal levels.