TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F − MARCH 1988 − REVISED MAY 1995

6

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

analog input

Two sets of analog inputs are provided. Normally, the IN+ and IN− input set is used; however, the auxiliary input

set, AUX IN + and AUX IN−, can be used if a second input is required. Each input set can be operated in either

differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain

for the IN +, IN−, AUX IN +, and AUX IN− inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either

input circuit can be selected via software control. It is important to note that a wide dynamic range is assured

by the differential internal analog architecture and by the separate analog and digital voltage supplies and

grounds.

A/D bandpass filter, A/D bandpass filter clocking, and A/D conversion timing

The A/D high-pass filter can be selected or bypassed via software control. The frequency response of this filter

is presented in the following pages. This response results when the switched-capacitor filter clock frequency

is 288 kHz and the A/D sample rate is 8 kHz. Several possible options can be used to attain a 288-kHz

switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the low-pass filter transfer function

is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The ripple bandwidth and 3-dB

low-frequency roll-off points of the high-pass section are 150 Hz and 100 Hz, respectively. However, the

high-pass section low-frequency roll-off is frequency scaled by the ratio of the A/D sample rate to 8 kHz.

The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many

options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX

counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master

clock input frequencies.

The A/D conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter

clock with the RX counter B. Unwanted aliasing is prevented because the A/D conversion rate is an integral

submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are synchronously

locked.

A/D converter performance specifications

Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter

operating characteristics section of this data sheet. The realization of the A/D converter circuitry with

switched-capacitor techniques provides an inherent sample-and-hold.

analog output

The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs

are brought out. This amplifier can drive transformer hybrids or low-impedance loads directly in either a

differential or single-ended configuration.

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing

The frequency response of this filter is presented in the following pages. This response results when the

low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter

is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output

of the (sin x)/ x correction filter to eliminate the periodic sample data signal information, which occurs at multiples

of the 288-kHz switched-capacitor filter clock. The continuous time filter also greatly attenuates any

switched-capacitor clock feedthrough.