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HV7100NG-G Datasheet(PDF) 7 Page - Supertex, Inc |
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HV7100NG-G Datasheet(HTML) 7 Page - Supertex, Inc |
7 / 8 page 7 Supertex inc. www.supertex.com Doc.# DSFP-HV7100 B072413 HV7100 Pin Description Pin # Function Description 1 VDD Output of an internal linear voltage regulator, which in turn is powered by V PP. It provides power to the internal low-side (ground referenced) circuitry. An external voltage may be applied to this pin, provided it is higher than 3.6V but less than 5.5V. Bypass this pin with a 100nF ceramic capacitor to ground. 2 LIN A DC voltage ranging from 0.5 to 2.5V sets the duty cycle of the gate output from 0% to 100%. This input is immune to moderate noise on the control signal. 3 DIN0 Applying 0000 to 1111 to these logic input pins sets the duty cycle of the gate output from 0 to 100%. A 1-bit increment is equal to 6.67% increment in duty cycle. See Table 1 on page 5. 4 DIN1 5 DIN2 6 DIN3 7 EN Enable input. A logic high applied to this input enables the output. 8 GND Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train and logic return. 9 CT In conjunction with RT, a capacitor from this pin to ground sets PWM frequency. A triangle wave appears on this pin, with an amplitude of 0.5 - 2.5V and at the PWM frequency. 10 RT In conjunction with CT, a resistor from this pin to ground sets PWM frequency. 11 VGATE This is the output pin of the internal linear regulator that biases the gate drive circuit. Bypass with 100nF ceramic capacitor to VPP. 12 VPP1 Supply voltage pins. Both must be connected to the supply voltage (+24V/+48V). Connect together as close as possible to the IC. Bypass locally with a ceramic capacitor to ground. 13 VPP2 14 OUT This pin is the output gate driver for an external P-channel power MOSFET. |
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