3

HV66

Supertex inc.

www.supertex.com

Doc.# DSFP-HV66

C070313

Sym

Parameter

Min

Max

Units Conditions

I

DD

V

-

15

mA

V

I

PPQ

Quiescent V

-

0.5

mA

Outputs high

-

0.5

mA

Outputs low

I

DDQ

Quiescent V

-

0.5

mA

All V

V

OH

High-level output

HV

OUT

50

-

V

I

DATA OUT

4.6

-

I

V

OL

Low-level output

HV

OUT

-

8.0

V

I

DATA OUT

-

0.4

I

I

IH

High-level input current

-

1.0

µA

V

I

IL

Low-level input current

-

-1.0

µA

V

V

OLBP

Low-level output voltage, backplane

-

3.0

V

I

V

OHBP

High-level output voltage, backplane

57

-

V

I

O

C, logic input rise/fall time = 10ns.)

f

CLK

Clock frequency

-

5.0

MHz

---

t

Clock width high or low

100

-

ns

---

t

SU

Data set-up time before clock rises

25

-

ns

---

t

H

Data hold time after clock rises

50

-

ns

---

t

Time from latch enable or POL to HV

OUT

-

500

ns

C

t

Time from POL to BP

OUT

-

500

ns

C

t

DHL

Delay time clock to data high to low

-

200

ns

C

t

DLH

Delay time clock to data low to high

-

200

ns

C

t

DLE

Delay time clock to LE low to high

50

-

ns

---

t

WLE

Width of LE pulse

100

-

ns

---

t

SLE

LE set-up time before clock rises

50

-

ns

---

t

BP

10

1000

µs

C

|t

BP

-

100

µs

C

Power-up sequence should be the following:

1. Connect ground.

2. Apply V

3. Set all inputs (Data, CLK, EN, etc.) to a known state.

4. Apply V

The V

Power-down sequence should be the reverse of the above.