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CAT1161J-45TE13 Datasheet(PDF) 2 Page - Catalyst Semiconductor

Part # CAT1161J-45TE13
Description  Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
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Manufacturer  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT1161J-45TE13 Datasheet(HTML) 2 Page - Catalyst Semiconductor

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CAT1161/2
Doc. No. 3002, Rev. D
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC
Power Supply Current
fSCL = 100 KHz
3
mA
ISB
Standby Current
VCC = 3.3V
40
µA
VCC = 5
50
µA
ILI
Input Leakage Current
VIN = GND or VCC
2
µA
ILO
Output Leakage Current
VIN = GND or VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC X 0.7
VCC + 0.5
V
VOL1
Output Low Voltage (SDA)
IOL = 3 mA, VCC = 3.0V
0.4
V
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55
°C to +125°C
Storage Temperature ....................... –65
°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25
°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
°C
Output Short Circuit Current(2) ........................ 100 mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(3)(4)
Latch-Up
JEDEC Standard 17
100
mA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
PIN FUNCTIONS
Pin No. Pin Name
Function
1
DC
Do Not Connect
2
RESET
Active Low Reset I/O
3
WP
Write Protect
4
GND
Ground
5
SDA
Serial Data/Address
6
SCL
Clock Input
7
RESET
Active High Reset I/O
8VCC
Power Supply


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