TLK2208

8PORT GIGABIT ETHERNET TRANSCEIVER

SLLS556B − DECEMBER 2002 − REVISED NOVEMBER 2003

1

POST OFFICE BOX 655303

(Gbps) Synchronizable Transceivers

1.25 Gbps

No External Components Necessary.

PECL Compatible Levels

Preemphasis Levels

−

Nibble-Wide Double Data Rate (DDR)

Clocking Interface

−

Multiplexed Channel DDR Clock

Interface

Compensation

Compliant Encoder and Decoder

(Extendable to 2.5 V)

Outputs to Drive 50-

Ω Lines

−

Selectable Source Synchronous or

Source Centered Timing on Inputs

From MAC

−

Source Centered Timing on Outputs

to the MAC

Testability Features (PRBS Generation

and Verification, Serial Loopback, and

Far-End Loopback)

Interface (MDIO) Support

Required for PLLs

289-Terminal, 1,0-mm Ball-Pitch BGA

Technology

70

°C)

description

The TLK2208 is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high

port density and ultralow power in a small form-factor footprint. The TLK2208 provides for high-speed full-duplex

point-to-point data transmissions based on the IEEE 802.3z 1000-Mbps Ethernet specification. The TLK2208

supports data rates from 1.0 Gbps through 1.3 Gbps.

The primary application of this device is to provide building blocks for developing point-to-point baseband data

transmission over controlled impedance media of 50

Ω. The transmission media can be printed circuit board

traces, copper cables or fiber-optical interface modules. The ultimate rate and distance of data transfer is

dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2208 performs the data encoding, decoding, serialization, deserialization, clock extraction and clock

tolerance compensation functions for a physical layer interface device. Each channel operates at up to 1.3 Gbps

providing up to 8.32 Gbps of aggregate data bandwidth over copper or optical-media interfaces.

The TLK2208 supports two selectable reduced-pin-count double-data-rate (DDR) timing interfaces, nibble

mode and multiplexed channel mode, to a protocol device.

In the nibble interface mode, the parallel interface accepts nibble-wide unencoded or 8b/10b encoded data

aligned to both the rising and falling edges of the transmit clock.

In the multiplexed channel mode, the parallel interface accepts 8-bit-wide unencoded or 10-bit-wide 8b/10b

encoded data with channels A, C, E, and G aligned to the falling edge of the source synchronous transmit clock

and channels B, D, F, and H aligned to the rising edge of the transmit clock. The receive path interface is done

in the same manner.

Copyright

 2002 − 2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.