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TLK2711-SP Datasheet(PDF) 10 Page - Texas Instruments |
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TLK2711-SP Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 29 page  TXD0−TXD15 2 V 0.8 V 2 V 0.8 V TXCLK TKLSB, TKMSB, tsu th tf tr 0 V 3.6 V 0 V 3.6 V tr tf 10 TLK2711-SP SGLS307O – JULY 2006 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 7.7 Reference Clock (TXCLK) Timing Requirements over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Frequency Receiver data rate / 20 –100 100 ppm Frequency tolerance –100 100 ppm Duty cycle 40% 50% 60% Jitter Peak to peak 40 ps (1) Nonproduction tested parameters 7.8 TTL Output Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = –2 mA, VDD = MIN 2.1 2.3 V VOL Low-level output voltage IOL = 2 mA, VDD = MIN 0.25 0.5 V tr(slew) Slew rate (rising), magnitude of RXCLK, RKLSB, RKMSB, RXD0 to RXD15 0.8 V to 2 V, C = 5 pF, See Figure 2 0.5 V/ns tf(slew) Slew rate (falling), magnitude of RXCLK, RKLSB, RKMSB, RXD0 to RXD15 0.8 V to 2 V, C = 5 pF, See Figure 2 0.5 V/ns tsu RXD0 to RXD15, RKMSB, RKLSB setup to ↑ RXCLK 50% voltage swing, TXCLK = 80 MHz, See Figure 2 (1) 3 ns 50% voltage swing, TXCLK = 125 MHz, See Figure 2 (1) 2.5 th RXD0 to RXD15, RKMSB, RKLSB hold to ↑ RXCLK 50% voltage swing, TXCLK = 80 MHz, See Figure 2 (1) 3 ns 50% voltage swing, TXCLK = 125 MHz, See Figure 2 (1) 2 Figure 1. TTL Data Input Valid Levels for AC Measurements |
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Similar Description - TLK2711-SP |
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