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LP8731QYZRRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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LP8731QYZRRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 51 page  LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 7.5 General Electrical Characteristics Unless otherwise noted, VIN = 3.6 V. Typical values and limits apply for TJ = 25°C. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ VINLDO12 shutdown current VIN = 3.6 V 3 µA VPOR Power-on reset threshold VDD Falling Edge (2) 1.9 V TSD Thermal shutdown threshold 160 °C TSDH Thermal shutdown hysteresis 20 Rising 2.9 UVLO Undervoltage lockout V Falling 2.7 (1) All voltages are with respect to the potential at the GND pin. (2) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range. 7.6 Low Dropout Regulators, LDO1 And LDO2 Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF. Typical values and limits apply for TJ = 25°C. (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Operational voltage range VINLDO1 and VINLDO2 PMOS pins(4) 2.45(5) 5.5(5) V VOUT Output voltage accuracy (default Load current = 1 mA −3%(5) 3%(5) Accuracy VOUT) VIN = (VOUT + 0.3 V) to 5 V (6) Line regulation 0.2(5) %/V Load current = 1 mA ΔVOUT VIN = 3.6 V, Load regulation 0.011(5) %/mA Load current = 1 mA to IMAX ISC Short circuit current limit LDO1 to LDO2, VOUT = 0 V 500 mA Load current = 50 mA at VOUT = 2.8 V (7) 30 50(5) VIN – VOUT Dropout voltage mV Load current = 250 mA at VOUT = 2.8 V 150 200(5) PSRR Power supply ripple rejection ƒ = 10 kHz, Load current = IMAX 45 dB θn Supply output noise 10 Hz < F < 100 KHz 280 µVrms Quiescent current “on” IOUT = 0 mA 40 µA IQ (8) (9) Quiescent current “on” IOUT = IMAX 60 µA Quiescent current “off” EN is de-asserted(10) 0.03 µA TON Turn-on time Start-up from shutdown 300 µs Capacitance for stability 0°C ≤ TJ ≤ 125°C 0.33 0.47 µF COUT Output capacitance −40°C ≤ TJ ≤ 125°C 0.68 1 µF ESR 5 500 m Ω (1) All voltages are with respect to the potential at the GND pin. (2) Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. (3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. (4) Pins A1 and/or A5 can operate from VIN min of 1.74 to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. However, if VIN is required to operate at a higher voltage than other device supply pins, it is necessary to wire the VINLDO12 pins (B4 an B5) and VINLDO1 and VINLDO2 pins (A1 and/or A5) together to that higher voltage so that the LDO core supply has sufficient head-room to operate the gate of the PMOS. (5) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C. (6) VIN minimum for line regulation values is 1.8 V. (7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. (8) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. (9) The IQ can be defined as the standing current of the LP8731-Q1 when the I 2C bus is activated and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP8731-Q1 is powered using a battery. (10) The IQ exhibits a higher current draw when the EN pin is de-asserted because the I 2C buffer pins draw an additional 2 µA. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 |
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