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LP55231 Datasheet(PDF) 7 Page - Texas Instruments |
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LP55231 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 57 page  7 LP55231 www.ti.com SNOSCR5B – MARCH 2013 – REVISED MAY 2016 Product Folder Links: LP55231 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated (1) Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD. (2) The ideal external clock signal for the LP55231 is a 0-V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz, program execution is faster, and at frequencies below 32.7 kHz program execution is slower. 6.10 Recommended External Clock Source Conditions See (1) (2) MIN NOM MAX UNIT LOGIC INPUT CLK ƒCLK Clock frequency 32.7 kHz tCLKH High time 6 µs tCLKL Low time 6 µs tr Clock rise time 10% to 90% 2 µs tf Clock fall time 90% to 10% 2 µs (1) Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD. 6.11 Serial Bus Timing Parameters (SDA, SCL) See (1) and Figure 2 MIN MAX UNIT ƒSCL Clock frequency 400 kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Setup time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 20 + 0.1 Cb 300 ns 8 Fall time of SDA and SCL 15 + 0.1 Cb 300 ns 9 Setup time for STOP condition 600 ns 10 Bus free time between a STOP and a START condition 1.3 µs Cb Capacitive load parameter for each bus line Load of 1 pF corresponds to one nanosecond. 10 200 ns Figure 1. External Clock Signal Figure 2. Timing Parameters |
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