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AN4137 Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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AN4137 Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 20 page AN4137 APPLICATION NOTE 8 ©2003 Fairchild Semiconductor Corporation where Ids peak is specified in equation (8), f s is the FPS switching frequency, Llk is the leakage inductance, Vsn is the snubber capacitor voltage at the minimum input voltage and full load condition, VRO is the reflected output voltage and Rsn is the snubber resistor. Vsn should be larger than VRO and it is typical to set Vsn to be 2~2.5 times of VRO. Too small a Vsn results in a severe loss in the snubber network as shown in equation (26). The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as where fs is the FPS switching frequency. In general, 5~10% ripple is reasonable. The snubber capacitor voltage (Vsn) of equation (26) is for the minimum input voltage and full load condition. When the converter is designed to operate in CCM, the peak drain cur- rent together with the snubber capacitor voltage decrease as the input voltage increases. The snubber capacitor voltage under maximum input voltage and full load condition is obtained as where fs is the FPS switching frequency, Llk is the primary side leakage inductance, VRO is the reflected output voltage, Rsn is the snubber resistor and Ids2 is the peak drain current at the maximum input voltage and full load condition. When the converter operates in CCM at the maximum input voltage and full load condition (refer to equation (12)), the Ids2 of equation (28) is obtained as When the converter operates in DCM at the maximum input voltage and full load condition (refer to equation (12)), the Ids2 of equation (28) is obtained as where Pin, VDC max, V RO and Lm are specified in equations (1), (4), (5) and (7), respectively, and fs is the FPS switching frequency. From equation (28), the maximum voltage stress on the inter- nal MOSFET is given by where VDC max is specified in equation (4). Check if Vds max is below 90% of the rated voltage of the MOSFET (BVdss) as shown in figure 11. The voltage rating of the snubber diode should be higher than BVdss. Usually, an ultra fast diode with 1A current rating is used for the snubber network. In the snubber design in this section, neither the lossy dis- charge of the inductor nor stray capacitance is considered. In the actual converter, the loss in the snubber network is less than the designed value due to this effects. Figure 10. Circuit diagram of the snubber network Figure 11. MOSFET drain voltage and snubber capacitor voltage P sn V sn () 2 R sn ----------------- 1 2 ---f sLlK Ids peak () 2 sn V V sn V RO – --------------------------- = = (26) ∆V sn V sn1 C sn Rsnfs ------------------------ = (27) V sn2 V RO V RO () 2 2R snLlkfs Ids2 () 2 + + 2 -------------------------------------------------------------------------------------------- = (28) I ds2 P in V DC max V RO + ⋅ V DC max V RO ⋅ ------------------------------------------------------------------ V DC max V RO ⋅ 2L mfs V DC max V RO + ⋅ ----------------------------------------------------------------------------- + = (29) I ds2 2P in ⋅ f s L m ⋅ ---------------- = (30) V ds max V DC max V sn2 + = (31) Np R sn C sn - V sn + V DC + - D sn Drain GND FPS C DC - V RO + + V ds - L lk V X X 0 V V DC max V RO V sn2 Effect of stray inductance (5-10V) BVdss Voltage Margin > 10% of BVdss |
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