AN4137

APPLICATION NOTE

8

©2003 Fairchild Semiconductor Corporation

snubber capacitor voltage at the minimum input voltage and

shown in equation (26). The leakage inductance is measured

at the switching frequency on the primary winding with all

other windings shorted.

Then, the snubber resistor with proper rated wattage should

be chosen based on the power loss. The maximum ripple of

the snubber capacitor voltage is obtained as

ripple is reasonable.

the minimum input voltage and full load condition. When the

converter is designed to operate in CCM, the peak drain cur-

rent together with the snubber capacitor voltage decrease as

the input voltage increases. The snubber capacitor voltage

under maximum input voltage and full load condition is

obtained as

the maximum input voltage and full load condition. When

the converter operates in CCM at the maximum input voltage

equation (28) is obtained as

When the converter operates in DCM at the maximum input

voltage and full load condition (refer to equation (12)), the

frequency.

From equation (28), the maximum voltage stress on the inter-

nal MOSFET is given by

MOSFET (BVdss) as shown in figure 11. The voltage rating

of the snubber diode should be higher than BVdss. Usually,

an ultra fast diode with 1A current rating is used for the

snubber network.

In the snubber design in this section, neither the lossy dis-

charge of the inductor nor stray capacitance is considered. In

the actual converter, the loss in the snubber network is less

than the designed value due to this effects.

Figure 10. Circuit diagram of the snubber network

Figure 11. MOSFET drain voltage and snubber capacitor

voltage

P

sn

V

sn

()

2

R

sn

-----------------

1

2

---f

peak

()

2

sn

V

V

sn

V

RO

–

---------------------------

=

=

(26)

sn

V

sn1

C

------------------------

=

(27)

V

sn2

V

RO

V

RO

()

2

2R

()

2

+

+

2

--------------------------------------------------------------------------------------------

=

(28)

I

ds2

P

in

V

DC

max

V

RO

+





⋅

V

DC

max

V

RO

⋅

------------------------------------------------------------------

V

DC

max

V

RO

⋅

2L

V

DC

max

V

RO

+





⋅

-----------------------------------------------------------------------------

+

=

(29)

I

ds2

2P

in

⋅

f

s

L

m

⋅

----------------

=

(30)

V

ds

max

V

DC

max

V

sn2

+

=

(31)

Np

R

sn

C

sn

-

V

sn

+

V

DC

+

-

D

sn

Drain

GND

FPS

C

DC

-

V

RO

+

+

V

ds

-

L

lk

V

X

X

0 V

V

DC

max

V

RO

V

sn2

Effect of stray inductance (5-10V)

BVdss

Voltage Margin > 10% of BVdss