TLV5590

2BIT ANALOGTODIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS134B − NOVEMBER 1995 − REVISED NOVEMBER 1996

11

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PRINCIPLES OF OPERATION

fast-acquisition-mode attack and decay times

counter is incremented or decremented by a count of 4 on every clock cycle when the input signal amplitude

is greater or less than the peak and valley DAC output voltage.

counter is decrement or increment by a count of 8 on every clock cycle when the input signal amplitude is less

or greater than the peak and valley DAC output voltage.

When the device is in fast aquistion mode then the decay counter is reset to 1.

are given in Table 5.

Table 5. Fast Acquisition Mode Attack and Decay Times

DESCRIPTION

CONDITIONS

MIN

MAX

UNIT

Attack Rate (ATTR)

TRACKINH = Low

1620

1980

mV/ms

Decay Rate (DECR)

TRACKINH = Low

3240

3960

mV/ms

hold mode

In hold mode the peak and valley counters are disabled from counting when either attack or decay enable

signals are present. There is no change to the peak and valley DAC output voltages in this mode.

When the device is in hold mode then the decay counter is reset to 1.

off mode

In the off mode the peak and valley counters are disabled from counting, and the device is set into low power

the DAC structure is isolated from the GND supply to conserve power. When the off state is released the peak

and valley voltages return to the previously set values.

When the device is in off mode then the decay counter is reset to 1.

test

The TEST input allows access to internal circuitry for production testing purposes and the pager system debug.

For normal operation, TEST should be tied to ground. For the debug and test mode, the TEST input should be

held high. The various operating modes are described in the following sections.