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TLV5580IDW Datasheet(PDF) 2 Page - Texas Instruments |
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TLV5580IDW Datasheet(HTML) 2 Page - Texas Instruments |
2 / 38 page TLV5580 8BIT, 80 MSPS LOW POWER A/D CONVERTER SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com 2 FUNCTIONAL BLOCK DIAGRAM SHA DAC ADC + − ADC Correction Logic Output Buffers 22 2 2 2 D0(LSB)−D7(MSB) 2 2 SHA SHA SHA SHA SHA The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction logic ensures no missing codes over the full operating temperature range. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLV5580 SOIC, 28 DW 0 °C to +70°C TLV5580C TLV5580CDW Rails, 20 ″ ″ ″ ″ ″ TLV5580CDWR Tape and Reel, 1000 TLV5580 TSSOP. 28 PW 0 °C to +70°C TV5580 TLV5580CPW Rails, 20 ″ ″ ″ ″ ″ TLV5580CPWR Tape and Reel, 2000 TLV5580 SOIC, 28 DW −40 °C to +85°C TLV5580I TLV5580IDW Rails, 50 ″ ″ ″ ″ ″ TLV5580IDWR Tape and Reel, 1000 TLV5580 TSSOP, 28 PW −40 °C to +85°C TY5580 TLV5580IPW Rails, 50 ″ ″ ″ ″ ″ TLV5580IPWR Tape and Reel, 2000 (1) For the most current specifications and package information, refer to our web site at www.ti.com. |
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