UCC1806

UCC2806

UCC3806

SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006

7

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DETAILED PIN DESCRIPTIONS (continued)

CURLIM: CURLIM programs the primary current limit threshold and determines whether the device latches off

or retries after an overcurrent condition. When a shutdown signal is generated, a 200-μA current source to

ground pulls down on CURLIM. If the voltage on the pin remains above 350 mV the device remains latched and

the power must be cycled to restart. If the voltage on the pin falls below 350 mV, the device attempts a restart.

adjust voltage threshold the following equations can be used.

Current limit adjust latching mode voltage is calculated in equation (2)

V =

1 +

> 350 mV

Current limit adjust non-latching mode voltage is calculated in equation (3)

V =

1 +

< 350 mV

where

D

R1 is the resistance from the VREF to CURLIM

D

R2 is the resistance from CURLIM to GND

GND: GND is the reference ground and power ground for all functions of this part. Bypass and timing capacitors

should be connected as close as possible to GND.

RT: RT is the connection point for the oscillator timing resistor. It has a low impedance input and is nominally

at 1.25 V. The current through RT is mirrored to the timing capacitor pin, CT. This causes a linear charging of

than 12.5 kΩ.

SYNC: SYNC is a bi-directional pin, allowing or providing external synchronization with TTL compatible

thresholds. In a typical application RT is connected through a timing resistor to GND which allows the internal

oscillator to free run. In this mode SYNC outputs a TTL compatible pulse during the oscillator dead time (when

CT is being discharged). If RT is forced above 4.4 V, SYNC acts as an input with TTL compatible thresholds

and the internal oscillator is disabled. When SYNC is high, greater than 2 V the outputs are held active low.

When SYNC returns low, the outputs may be high until the on--time is terminated by the normal peak current

signal, a fault seen at SHUTDOWN or the next high assertion of SYNC. Multiple UCC3806s can be

synchronized by a single master UCC3806 or external clock.

VC: VC is the input supply connection for the FET drive outputs and has an input range from 2.5 V to 15 V. VC

should be capacitively bypassed for proper operation.

VIN: VIN is the input supply connection for this device. The UCC1806 has a maximum startup threshold of 8 V

and internally limited by means of a 15 V shunt regulator. The shunted supply current must be limited to 25 mA.

For proper operation, VIN must be bypassed to GND with at least a 0.01-μF ceramic capacitor

VREF:VREF is a 5.1 V ±1% trimmed reference output with a 5 mA maximum available current. VREF must be

bypassed to GND with at least a 0.1-μF ceramic capacitor for proper operation.

(2)

(3)