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UCC2580D-3G4 Datasheet(PDF) 7 Page - Texas Instruments

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Part # UCC2580D-3G4
Description  Single Ended Active Clamp/Reset PWM
Download  18 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UCC2580D-3G4 Datasheet(HTML) 7 Page - Texas Instruments

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UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
Output Configurations
The UCC3580 family of ICs is designed to provide con-
trol functions for single ended active clamp circuits. For
different implementations of the active clamp approach,
different drive waveforms for the two switches (main and
auxiliary) are required. The -3 and -4 versions of the IC
supply
complementary
non-overlapping
waveforms
(OUT1 and OUT2) with programmable delay which can
be used to drive the main and auxiliary switches. Most
active clamp configurations will require one of these out-
puts to be transformer coupled to drive a floating switch
(e.g. Figure 5). The -1 and -2 versions have the phase of
OUT2 inverted to give overlapping waveforms. This con-
figuration is suitable for capacity coupled driving of a
ground referenced p-channel auxiliary switch with the
OUT2 drive while OUT1 is directly driving an n-channel
main switch (e.g. Figure 4).
The programmable delay can be judiciously used to get
zero voltage turn-on of both the main and auxiliary
switches in the active clamp circuits. For the UCC3580,
a single pin is used to program the delays between
OUT1 and OUT2 on both sets of edges. Figure 1 shows
the relationships between the outputs. Figure 2 gives the
ratio between the two delays. During the transition from
main to auxiliary switch, the delay is not very critical for
ZVS turn-on. For the first half of OUT1 off-time, the body
diode of the auxiliary switch conducts and OUT2 can be
turned on any time. The transition from auxiliary to main
switch is more critical. Energy stored in the parasitic in-
ductance(s) at the end of the OUT2 pulse is used to dis-
charge the parasitic capacitance across the main switch
during the delay time. The delay (Delay 1) should be op-
timally programmed at 1/4 the resonant period deter-
mined by parasitic capacitance and the resonant
inductor (transformer leakage and/or magnetizing induc-
tances, depending on the topology). However, depend-
ing on other circuit parasitics, the resonant behavior can
change, and in some cases, ZVS turn-on may not be ob-
tainable. It can be shown that the optimum delay time is
independent of operating conditions for a specific circuit
and should be determined specifically for each circuit.
APPLICATION INFORMATION (cont.)
Figure 4. Active clamp forward converter.
UDG-95071-2


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