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UCC2897RTJT Datasheet(PDF) 7 Page - Texas Instruments

Part # UCC2897RTJT
Description  ADVANCED CURRENT-MODE ACTIVE CLAMP PWM CONTROLLER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UCC2897RTJT Datasheet(HTML) 7 Page - Texas Instruments

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UCC2897
SLUS591G − NOVEMBER 2003 − REVISED DECEMBER 2008
7
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
UCC2897
I/O
DESCRIPTION
AUX
14
O
This output drives the auxiliary clamp P−channel MOSFET which is turned on when the main PWM
switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-
on current and 2-A sink turn-off current.
CS
9
I
This pin is used to sense the peak current utilized for current mode control and for current limiting func-
tions. The peak signal which can be applied to this pin before pulse-by-pulse current limiting activates
is approximately 0.50 V for the UCC2897.
FB
11
I
This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM
control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoupler is used to pull the
control pin closer to GND to reduce the pulse width of the OUT output driving the main power switch of
the converter.
GND
8
This pin serves as the fundamental analog ground for the PWM control circuitry. This pin should be
connected to PGND directly at the device.
LINEOV
19
I
Provides the LINE overvoltage function.
LINEUV
18
I
This pin provides a means to accurately enable/disable the power converter stage by monitoring the
bulk input voltage or another parameter. When the circuit initially starts (or restarts from a disabled
condition), a rising input on LINEUV enables the outputs when the threshold of 1.27 V is crossed. After
the circuit is enabled, then a falling LINEUV signal disables the outputs when the same threshold is
reached. The hysteresis between the two levels is programmed using an internal current source.
OUT
15
O
This output pin drives the main PWM switching element MOSFET in an active clamp controller. It can
directly drive an N-channel device with 2-A source turn-on current and 2-A sink turn-off current.
PGND
13
The PGND should serve as the current return for the high-current output drivers OUT and AUX. Ideally,
the current path from the outputs to the switching devices, and back would be as short as possible, and
enclose a minimal loop area.
PVDD
16
I
This is the supply pin for the power devices in the IC. It is separated internally from the VDD pin.
RSLOPE
10
I
A resistor connected from this pin to GND programs an internal current source that sets the slope com-
pensation ramp for the current mode control circuitry.
RTDEL
3
I
A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to accommo-
date the resonant transitions of the active clamp power converter.
RTOFF
5
I
A resistor connected from this pin to GND programs an internal current source that discharges the in-
ternal timing capacitor.
RTON
4
I
A resistor connected from this pin to GND programs an internal current source that charges the internal
timing capacitor.
SS/SD
12
I
A capacitor from SS/SD to ground is charged by an internal current source of IRTON to program the
soft-start interval for the controller. During a fault condition this capacitor is discharged by a current
source equal to IRTON.
SYNC
7
I
The SYNC pin serves as a bidirectional synchronization input/output for the internal oscillator. The syn-
chronization function is implemented such that the user programmable maximum duty cycle (set by
RTON and RTOFF) remains accurate during synchronized operation.
VDD
17
I
This is the power supply for the device. There should be a minimum 0.1-
µF capacitor directly from VDD
to PGND.
VIN
1
I
This pin is connected to the input power rail directly. Inside the device, a high-voltage start-up device is
utilized to provide the start-up current for the controller until a bootstrap type bias rail becomes avail-
able.
VREF
6
O
This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA. Since this refer-
ence provides the supply rail for internal logic, it should be bypassed to AGND as close as possible to
the device.


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