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UCC3588PWG4 Datasheet(PDF) 4 Page - Texas Instruments |
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UCC3588PWG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 15 page UCC3588 5BIT PROGRAMMABLE OUTPUT BiCMOS POWER SUPPLY CONTROLLER SLUS311A – JULY 1999 – REVISED AUGUST 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, TA = 0°C to 70°C. TA = TJ. VCC = 12 V, RT = 49 k, (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DAC / Reference Section COMMAND voltage accuracy 10.8 V < VCC < 13.2 V, measured on COMP, 0 °C < TA < 70°C, See Note 2 –1.0 1.0 % D0 to D4 voltage high 5.5 6 6.5 V D0 to D4 voltage threshold 2.5 3.0 3.5 V D0 to D4 voltage input bias current V(D4,...,D0) < 0.5 V –80 –100 mA Overvoltage Comparator Section Trip point % Over VCOMMAND, See Note 1 8 12 % Hysteresis 10 20 35 mV Undervoltage Comparator Section Trip point % Under VCOMMAND, See Note 1 –8.0 –12.0 % Hysteresis 10 20 35 mV PWRGOOD Signal Section Output impedance VCC = 12 V, IPWRGOOD = 1 mA 470 W Overvoltage Protection Section Trip point % Over VCOMMAND, See Note 1 15 17.5 20 % Hysteresis 20 35 mV VSENSE input bias current OV, OVP, UV combined –8 –12 –16 mA Gate Drivers (DRVHI, DRVLO) Section Output high voltage IGATE = 100 mA, VCC = 12 V 10.8 11.5 V Output low voltage IGATE =–100 mA, VCC = 12 V 0.5 0.8 V Driver non-overlap time (DRVHI– to DRVLO+) See Note 3 90 120 150 ns Driver non-overlap time (DRVLO– to DRVHI+) See Note 3 50 80 120 ns Driver rise time 3 nF capacitive load 80 100 ns Driver fall time 3 nF capacitive load 80 100 ns Current Limit Section Start of quick charge to shutdown threshold VISNS = VSENSE + 75 mV, CSS = 10 nF, See Note 4, See Note 5 50 ms Current limit threshold voltage VTHRESHOLD = VISNS – VVSENSE 40 54 70 mV ISNS input bias current –8 –12 –16 mA NOTES: 6. This percentage is measured with respect to the ideal command voltage programmed by the VID (D0,....,D4) pins and applies to all DAC codes from 1.3 V to 3.5 V. 7. Reference and error amplifier offset trimmed while the voltage amplifier is set in unity gain mode. 8. Deadtime delay is measured from the 50% point of DRVHI falling to the 50% point of DRVLO rising, and vice-verse. 9. This time is dependent on the value of CSS. 10. Ensured by design. Not 100% production tested. |
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