Electronic Components Datasheet Search |
|
MT8981DE Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc |
|
MT8981DE Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc |
11 / 17 page ISO-CMOS MT8981D 2-27 † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i. Figure 12 - Frame Alignment Figure 13 - Clock Timing AC Electrical Characteristics† - Clock Timing (Figures 12 and 13) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 I N P U T S Clock Period* tCLK 220 244 300 ns 2 Clock Width High tCH 95 122 150 ns 3 Clock Width Low tCL 110 122 150 ns 4 Clock Transition Time tCTT 20 ns 5 Frame Pulse SetupTime tFPS 20 200 ns 6 Frame Pulse Hold Time tFPH 0.020 50 µs 7 Frame Pulse Width tFPW 244 ns tCLK tCTT tCH tCHL tCTT tFPH tFPS tFPH tFPS tFPW tCL C4i F0i 2.0V 0.8V 2.0V 0.8V C4i F0i BIT CELLS Channel 31 Bit o Channel 0 Bit 7 |
Similar Part No. - MT8981DE |
|
Similar Description - MT8981DE |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |