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TM4CN64EFN Datasheet(PDF) 8 Page - Texas Instruments |
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TM4CN64EFN Datasheet(HTML) 8 Page - Texas Instruments |
8 / 15 page TM2CN64EFN 2097152 BY 64BIT TM4CN64EFN 4194304 BY 64BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS714 − MAY 1998 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements† ’xCN64EFN-10 UNIT MIN MAX UNIT tCK2 Cycle time, CLK, CAS latency = 2 15 ns tCK3 Cycle time, CLK, CAS latency = 3 10 ns tCH Pulse duration, CLK high 3 ns tCL Pulse duration, CLK low 3 ns tAC2 Access time, CLK high to data out, CAS latency = 2 (see Note 8) 8 ns tAC3 Access time, CLK high to data out, CAS latency = 3 (see Note 8) 7.5 ns tOH Hold time, CLK high to data out 3 ns tLZ Delay time, CLK high to DQ in low-impedance state (see Note 9) 2 ns tHZ Delay time, CLK high to DQ in high-impedance state (see Note 10) 8 ns tIS Setup time, address, control, and data input 3 ns tIH Hold time, address, control, and data input 1 ns tCESP Power-down/self-refresh exit time 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 50 100 000 ns tRC Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command 80 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 20 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 20 ns tAPR Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP − (CL −1) * tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tRP + tCK ns tT Transition time (see Note 12) 1 5 ns tREF Refresh interval 64 ms nCCD Delay time, READ or WRT command to an interrupting command 1 cycle nCDD Delay time, CS low or high to input enabled or inhibited 0 0 cycle nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 cycle nCWL Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P 1 cycle nDID Delay time, ENBL or MASK command to enabled or masked data in 0 0 cycle nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 cycle nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 2 cycle nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 3 cycle nWCD Delay time, WRT command to first data in 0 0 cycle nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle † All references are made to the rising transition of CK unless otherwise noted. NOTES: 8. tAC is referenced from the rising transition of CK that precedes to the data-out cycle. For example, the first-data out tAC is referenced from the rising transition of CK that is CAS latency − one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CK that is CAS latency − one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL. |
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