TM8TT64JPN, TM16TT64JPN

TM8TT72JPN, TM16TT72JPN

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS700A − APRIL 1998 − REVISED AUGUST 1998

11

POST OFFICE BOX 1443

’xTTxxJPN-8

’xxTTxxJPN-8A

UNIT

MIN

MAX

MIN

MAX

UNIT

tCK2

Cycle time, CK

CAS latency = 2

10

15

ns

tCK3

Cycle time, CK

CAS latency = 3

8

8

ns

tCH

Pulse duration, CK high

3

3

ns

tCL

Pulse duraction, CK low

3

3

ns

tAC2

Access time, CK high to data out

(see Note 11)

CAS latency = 2

6

7.5

ns

tAC3

Access time, CK high to data out

(see Note 11)

CAS latency = 3

6

6

ns

tOH

Hold time, CK high to data out with 50-pF load

3

3

ns

tLZ

Delay time, CK high to DQ in low-impedance state

(see Note 12)

1

1

ns

tHZ

Delay time, CK high to DQ in high-impedance state

(see Note 13)

8

8

ns

tIS

Setup time, address, control, and data input

2

2

ns

tIH

Hold time, address, control, and data input

1

1

ns

tIH

Hold time, address, control, and data input

1

1

ns

tCESP Power down/self−refresh exit time

8

8

ns

tRAS

Delay time, ACTV command to DEAC or DCAB command

48

100 000

48

ns

tRC

Delay time, ACTV,MRS,REFR,or SLFR to ACTV,MRS,REFR,or SLFR command

68

68

ns

tRCD

Delay time ACTV command to READ,READ−P,WRT,or WRT−P command (see

Note 14)

20

20

ns

tRP

Delay time, DEAC or DCAB command to ACTV,MRS,REFR, or SLFR command

20

20

ns

tRRD

Delay time,ACTV command in one bank to ACTV command in the other bank

16

16

ns

tRSA

Delay time,MRS command to ACTV,MRS,REFR,or SLFR command

16

16

ns

tAPR

Final data out of READ−P operation to ACTV,MRS,SLFR,or REFR command

tRP −(CL−1)*tCK tRP − (CL−1)* tCK

ns

tAPW

Final data in of WRT−P operation to ACTV,MRS,SLFR,or REFR command

tRP + 1 tCK

tRP + 1 tCK

ns

tT

Transition time

1

5

1

5

ms

tREF

Refresh interval

64

64

ms

tREF

Refresh interval

64

64

ms

nCCD

Delay time, READ or WRT command to an interrupting command

1

1

cycles

nCCD

Delay time, READ or WRT command to an interrupting command

1

1

cycles

nCDD

Delay time, CS low or high to input enabled or inhibited

0

0

0

0

cycles

nCLE

Delay time, CKE high or low to CLK enabled or disabled

1

1

1

1

cycles

nCWL

Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P

1

1

cycles

nDID

Delay time, ENBL or MASK command to enabled or masked data in

0

0

0

0

cycles

nDOD

Delay time, ENBL or MASK command to enabled or masked data out

2

2

2

2

cycles

nHZP2

Delay

time,

DEAC

or

DCAB,

command

to

DQ

in

high-impedance state

CAS latency = 2

2

2

cycles

† All references are made to the rising transition of CK unless otherwise noted.

‡ Specifications in this table represent a single SDRAM device.

NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced

from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output

reference level 1.4 V.

12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command).

13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.

14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.