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TMDS181I Datasheet(PDF) 11 Page - Texas Instruments |
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TMDS181I Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 59 page  11 TMDS181, TMDS181I www.ti.com SLASE75C – AUGUST 2015 – REVISED JULY 2016 Product Folder Links: TMDS181 TMDS181I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted 6.8 DDC, I 2C, HPD, and ARC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT DDC AND I2C VI-DC SCL/SDA_SNK, SCL/SDA_SRC DC input voltage –0.3 5.5 V SCL/SDA_CTL, DC input voltage –0.3 3.6 V VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V SCL/SDA_CTL Low level input voltage 0.3 x VCC V VIH SCL/SDA_SNK, SCL/SDA_SRC high level input voltage 3 V SCL/SDA_CTL high level input voltage 0.7 x VCC V VOL SCL/SDA_CTL, SCL/SDA_SRC low level output voltage I0 = 3 mA and VCC > 2 V 0.4 V I0 = 3 mA and VCC < 2 V 0.2 x VCC fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF HPD VIH High-level input voltage HPD_SNK 2.1 V VIL Low-level input voltage HPD_SNK 0.8 V VOH High-level output voltage IOH = –500 µA; HPD_SRC, 2.4 3.6 V VOL Low-level output voltage IOL = 500 µA; HPD_SRC, 0 0.1 V ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V; 40 μA IH_HPD High-level input current Device powered; VIH = 5 V; IH_HPD includes RpdHPD resistor current 40 µA Device powered; VIL = 0.8 V; IL_HPD includes RpdHPD resistor current 30 RpdHPD HPD input termination to GND VCC = 0 V 150 190 220 k Ω SPDIF AND ARC VEL Operating DC voltage for single mode ARC output Test at ARC_OUT, see Figure 22 0 5 V VIN_DC Operating DC voltage for SPDIF input 0.05 V VSP_SW Signal amplitude of SPDIF input 0.2 0.5 0.6 V VElSWING Signal amplitude on the ARC output Test at ARC_OUT, 55 Ω external termination resistor, see Figure 22 0.4 0.5 0.6 V CLK_ARC Signal frequency on ARC Test at ARC_OUT, see Figure 22 3.687 5.645 ±0.1% 13.517 MHz Duty cycle Output clock duty cycle 45% 50% 55% Data rate SPDIF input DR 7.373 11.29 27.034 Mbps tEDGE Rise/fall time for ARC output From 10% to 90% voltage level 0.4 UI R_IN_SPDIF Input termination resistance for SPDIF 75 Ω Rest Single mode output termination resistance 0.1 MHz to 128× the maximum frame rate 36 55 75 Ω |
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Similar Description - TMDS181I |
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