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TMDS181IRGZR Datasheet(PDF) 10 Page - Texas Instruments |
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TMDS181IRGZR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 59 page  10 TMDS181, TMDS181I SLASE75C – AUGUST 2015 – REVISED JULY 2016 www.ti.com Product Folder Links: TMDS181 TMDS181I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted 6.7 TMDS Differential Output Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT VOH Single-ended high level output voltage Data rate ≤1.65 Gbps PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 10 VCC + 10 V Single-ended high level output voltage Data rate >1.65 Gbps and <3.4 Gbps PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC-200 VCC + 10 Single-ended high level output voltage Data rate >3.4 Gbps and < 6 Gbps(2) PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 400 VCC + 10 VOL Single-ended low level output voltage Data rate ≤1.65 Gbps PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 600 VCC – 400 V Single-ended low level output voltage Data rate >1.65 Gbps and <3.4 Gbps PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC – 700 VCC – 400 Single-ended low level output voltage Data rate >3.4 Gbps and < 6 Gbps(2) PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 1000 VCC – 400 VSWING_DA Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC/L; OE = H; DR = 270 Mbps/2.97/6 Gbps VSadj = 7.06 kΩ; 400 500 600 mV VSWING_CLK Single-ended output voltage swing on clock lane PRE_SEL = NC; TX_TERM_CTL = H; OE = H; Data rate ≤ 3.4 Gbps; VSadj = 7.06 kΩ; 400 500 600 mV PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; Data rate > 3.4 Gbps; VSadj = 7.06 kΩ; 200 300 400 ΔVSWING Change in single-end output voltage swing per 100 Ω ΔVSadj 20 mV ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5 mV VOD(PP) Output differential voltage before pre-emphasis VSADJ = 7.06 kΩ; PRE_SEL = NC see Figure 10 800 1200 mV VOD(SS) Steady state output differential voltage VSADJ = 7.06 kΩ; PRE_SEL = L, see Figure 11 600 1075 mV VOD_range Total TMDS data lanes output differential voltage for HDMI2.0. Retimer Mode Only See Figure 14 3.4 Gbps < Rbit ≤ 3.712 Gps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; 335 mV 3.712 Gbps < Rbit < 5.94 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; –19.66 × (Rbit 2) + (106.74 × Rbit) + 209.58 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; 150 IOS Short-circuit current limit Main link output shorted to GND 50 mA ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3 V through 50 Ω resistor; 45 μA RTERM Source termination resistance for HDMI2.0 75 150 Ω |
Similar Part No. - TMDS181IRGZR |
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Similar Description - TMDS181IRGZR |
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