15

8

7

6

4

3

0

15

0

TMS34094

ISA BUS INTERFACE

SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992

POST OFFICE BOX 1443

11

BPNT3–BPNT0 are used to index BKPORT to one of the bank select programming registers. BPNT3–BPNT0

will be incremented after each 16-bit access to BKPORT. BPNT3–BPNT0 are set to zero after reset. The

registers indexed by BPNT3–BPNT0 are summarized below.

BPNT3–BPNT0

BANK SELECT PROGRAMMING REGISTER

0000b

0000b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

Bank Address 0 Low (BKAD0L)

Bank Address 0 High (BKAD0H)

Bank Address 1 Low (BKAD1L)

Bank Address 1 High (BKAD1H)

Bank Address 2 Low (BKAD2L)

Bank Address 2 High (BKAD2H)

Bank Address 3 Low (BKAD3L)

Bank Address 3 High (BKAD3H)

Bank Select Mask 0 Low (BKMSK0L)

Bank Select Mask 0 High (BKMSK0H)

Bank Select Mask 1 Low (BKMSK1L)

Bank Select Mask 1 High (BKMSK1H)

Bank Select Mask 2 Low (BKMSK2L)

Bank Select Mask 2 High (BKMSK2H)

Bank Select Mask 3 Low (BKMSK3L)

Bank Select Mask 3 High (BKMSK3H)

Bit 0 of BKCTL is reserved. When writing to BKCTL, bit 0 must be set to 0.

SHDHCTL

RESERVED

IOUT

MSGOUT

IIN

MSGIN

This register shadows the least significant byte of the TMS34020s HSTCTLL register to allow the ISA host to

poll interrupts and/or messages without having to perform a host access to the TMS34020. This allows

handshaking without interrupting the TMS34020s operations. SHDHCTL cannot be written directly by the host;

it is only altered by host or TMS34020 cycles to HSTCTLL. The TMS34094 protects the IIN, MSGIN, IOUT, and

MSGOUT bits in much the same way as the TMS34020 protects the bits in HSTCTLL. Only the host writes of

HSTCTLL may alter MSGIN. Only TMS34020 writes can alter MSGOUT. ISA host writes may only set IIN or clear

IOUT. TMS34020 writes may only set IOUT and clear IIN.

SHDHCTL may not properly reflect the state of HSTCTLL if the TMS34020 is reset by setting the RST bit of

HSTCTLH.

HDATA

Host Data

In I/O mapped mode, this register is used to access the data transceiver for passing information between the

ISA host and the TMS34020 local memory. It is accessed as a 16-bit register from the ISA bus. The WS bit in

the HADDRL register determines whether the contents of the register is presented to the upper or lower half

of the LAD bus. HDATA is uninitialized after reset. HDATA may be affected by memory mapped accesses when

the IOE bit of MODECTL is set to 0.