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UCC29002DGKG4 Datasheet(PDF) 10 Page - Texas Instruments |
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UCC29002DGKG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 30 page 4 GND 3 VDD + Bias_OK VBIAS (Internal Bias) 14.2 V 4.375 V 10 UCC29002, UCC29002-1, UCC39002 SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016 www.ti.com Product Folder Links: UCC29002 UCC39002 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Feature Description (continued) In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the CS+ and CS − pins or when the bias voltage is below the minimum operating voltage. 7.3.9 Bias and Bias OK Circuit (VDD) The UCC39002 is built on a 15-V, high-performance BiCMOS process. Therefore, the maximum voltage across the VDD and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor. The current into the VDD pin must be limited to 10 mA as listed in Absolute Maximum Ratings. The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such, must be placed as close to the device pins (VDD and GND) as possible, using a good-quality, low-ESL capacitor, including trace length. The device is optimized for a capacitor value of 0.1 µF to 1 µF. Figure 4. VDD Clamp and Bias Monitor The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable function with a 4.375-V threshold. While VDD < 4.375 V the load share control functions are disabled. While this might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable in amplitude to the load share bus voltage, they can cause significant current distribution error in the system. The maximum voltage on the load share bus is limited approximately 1.7 V below the bias voltage level (VDD) which would result in an unacceptably low load share bus amplitude therefore poor accuracy at low VDD levels. To circumvent this potential design problem, the UCC39002 does not operate below the above mentioned 4.375-V bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002, TI recommends using an inexpensive charge pump which can generate the bias voltage for all the UCC39002s in the load share system. The maximum VDD of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as recommended in Figure 5. A Zener clamp on the VDD pin is provided internally so the device can be powered from higher voltage rails using a minimum number of external components. The CSA inputs must be adjusted so as to not exceed their absolute maximum voltage ratings. |
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