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TMS320DM357 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320DM357 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 195 page  1.2 Description TMS320DM357 Digital Media System-on-Chip SPRS553 – NOVEMBER 2008 www.ti.com • IEEE-1149.1 (JTAG) Boundary- • 0.09-µm/6-Level Cu Metal Process (CMOS) Scan-Compatible • 3.3-V and 1.8-V I/O, 1.2-V Core • Up to 71 General-Purpose I/O (GPIO) Pins • Applications: (Multiplexed With Other Device Functions) – Digital Media • 361-Pin Pb-Free BGA Package – Networked Media Encode/Decode (ZWT Suffix), 0.8-mm Ball Pitch – Video Imaging The TMS320DM357 (also referenced as DM357) leverages TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM357 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: • A coprocessor 15 (CP15) and protection module • Data and program Memory Management Units (MMUs) with table look-aside buffers. • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The DM357 performance is enhanced by its H.264/MPEG4/JPEG coprocessor (HMJCP). The HMJCP performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The H.264/MPEG4/JPEG coprocessor supports MPEG4 Simple Profile (SP) , D1, VGA, SIF encode/decode resolutions and JPEG encode/decode. The peripheral set includes: 2 configurable video ports (one input port and one output port); a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM357 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, and 1 Video Processing Back-End (VPBE) output for displaying video images. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM357. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. Digital Media System-on-Chip (DMSoC) 2 Submit Documentation Feedback |
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