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TMS320DM6441ZWT Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320DM6441ZWT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 236 page TMS320DM6441 SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 2-1. Characteristics of the Processor HARDWARE FEATURES DM6441 DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous (8/16-bit bus width) RAM, Flash Asynchronous EMIF (EMIFA) (NOR, NAND) Compact Flash MMC/SD with secure data input/output (SDIO) Flash Cards SmartMedia/xD Memory Stick/Memory Stick PRO 64 independent channels EDMA3 8 QDMA channels 2 64-bit general purpose (each configurable as 2 Timers separate 32-bit timers) 64-bit watch dog Peripherals UART 3 (one with RTS and CTS flow control) Not all peripherals pins SPI 1 (supports 2 slave devices) are available at the I2C 1 (master/slave) same time. (For more details, see Section 3, Audio Serial Port [ASP] 1 Device Configurations.) 10/100 Ethernet MAC with Management Data Input/Output 1 VLYNQ 1 HPI 1 (16-bit multiplexed address/data) General-Purpose Input/Output Port Up to 71 PWM 3 outputs ATA/CF 1 (ATA/ATAPI-5) 1 input (VPFE) Configurable Video Ports 1 output (VPBE) USB 2.0 High speed client VICP 1 Size (Bytes) 160KB RAM, 8KB ROM DSP • 32KB L1 program (L1P)/cache (up to 32KB) • 80KB L1 data (L1D)/cache (up to 32KB) • 64KB unified mapped RAM/cache (L2) On-Chip Memory Organization ARM • 16KB I-cache • 8KB D-cache • 16KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 C64x+ Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 (Silicon Revision 1.3 and earlier) Revision (address location: 0x0181 2000) 0x0003 (Silicon Revision 2.1 and later) JTAGID register 0x0B70 002F (Silicon Revision 1.3 and earlier) JTAG BSDL_ID (address location: 0x01C4 0028) 0x1B70 002F (Silicon Revision 2.1 and later) DSP 405 MHz , ARM 202.5 MHz at 1.05 V CPU Frequency MHz DSP 513 MHz, ARM 256 MHz at 1.2 V 10 Device Overview Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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