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TMS320DM6467T Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320DM6467T Datasheet(HTML) 8 Page - Texas Instruments |
8 / 352 page TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the TMS320DM6467T SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 3-1. Characteristics of the DM6467T Processor HARDWARE FEATURES DM6467T DDR2 Memory Controller DDR2 (Up to 400-MHz, 16/32-bit bus width) Asynchronous (8/16-bit bus width) RAM, Flash Asynchronous EMIF (EMIFA) (NOR, NAND) 64 independent channels EDMA 8 QDMA channels 2 64-Bit General Purpose (each configurable as 2 Timers separate 32-bit timers) 1 64-Bit Watchdog 3 (with SIR, MIR, CIR support and RTS/CTS flow UART control) (UART0 Supports Modem Interface) SPI 1 (supports 2 slave devices) I2C 1 (Master/Slave) 2 (one transmit/receive with 4 serializers, Multichannel Audio Serial Port (McASP) one DIT transmit only with 1 serializer for S/PDIF output) 10/100/1000 Ethernet MAC with Management Data 1 (with MII/GMII Interface) Input/Output (MDIO) Peripherals VLYNQ 1 Not all peripherals pins are General-Purpose Input/Output Port (GPIO) Up to 33 pins available at the same time PWM 2 outputs (for more detail, see the ATA 1 (ATA/ATAPI-6) Device Configurations section). PCI 1 (32-bit, 66 MHz) HPI 1 (16-/32-bit multiplexed address/data) 1 [horizontal and vertical downscaling, VDCE chroma conversion (4:2:2 ↔4:2:0)] Clock Recovery Generator (CRGEN) 1 Power Sleep Controller (PSC) 1 (peripheral/module clock gating) 2 8-bit BT.656 capture channels or 1 16-bit Y/C capture channel or 150-MHz Configurable Video Port Interface (VPIF) 1 8-/10-/12-bit raw video capture channel and 2 8-bit BT.656 display channels or 1 16-bit Y/C display channel MPEG transport stream interface 1 with 8-bit parallel or serial input and output Transport Stream Interface (TSIF) 1 with serial-only input and output Each with corresponding clock recovery generator (CRGEN) for external VCXO control. High- and Full-Speed Device USB 2.0 (1) High-, Full-, and Low-Speed Host (1) USB2.0 is not supported on -1G parts that are dated prior to May 1, 2010. See the TMS320DM6467T Silicon Errata (Literature Number: SPRZ307) for more details on how to decode the date from package markings. 8 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T |
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