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TMS320F241FN Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320F241FN Datasheet(HTML) 8 Page - Texas Instruments |
8 / 122 page TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions - F243 PGE Package NAME 144 LQFP TYPE† RESET STATE‡ DESCRIPTION NAME NO. TYPE† STATE‡ DESCRIPTION ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS ADCIN00 10 ADCIN01 8 ADCIN02 6 ADCIN03 4 I I Analog inputs to the ADC ADCIN04 3 I I Analog inputs to the ADC ADCIN05 144 ADCIN06 143 ADCIN07 139 VCCA 137 − − Analog supply voltage for ADC (5 V). It is highly recommended to isolate VCCA from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. VSSA 135 − − Analog ground reference for ADC VREFHI 141 − − ADC analog high-voltage reference input VREFLO 142 − − ADC analog low-voltage reference input EVENT MANAGER T1PWM/T1CMP/IOPB4 130 I/O/Z I Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO). T2PWM/T2CMP/IOPB5 128 I/O/Z I Timer 2 compare output/GPIO TDIR/IOPB6 85 I/O I Counting direction for general-purpose (GP) timer/GPIO. If TDIR=1, upward counting is selected. If TDIR=0, downward counting is selected. TCLKIN/IOPB7 87 I/O I External clock input for GP timer/GPIO. Note that timer can also use the internal device clock. CAP1/QEP0/IOPA3 123 I/O I Capture input #1/quadrature encoder pulse input #0/GPIO CAP2/QEP1/IOPA4 121 I/O I Capture input #2/quadrature encoder pulse input #1/GPIO CAP3/IOPA5 119 I/O I Capture input #3/GPIO PWM1/IOPA6 102 I/O/Z I Compare/PWM output pin #1 or GPIO PWM2/IOPA7 100 I/O/Z I Compare/PWM output pin #2 or GPIO PWM3/IOPB0 98 I/O/Z I Compare/PWM output pin #3 or GPIO PWM4/IOPB1 96 I/O/Z I Compare/PWM output pin #4 or GPIO PWM5/IOPB2 94 I/O/Z I Compare/PWM output pin #5 or GPIO PWM6/IOPB3 91 I/O/Z I Compare/PWM output pin #6 or GPIO PDPINT 89 I I Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINT is level-sensitive and can cause multiple interrupts when held low. † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS is enabled. NOTE: Bold, italicized pin names indicate pin function after reset. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 150 µA.) |
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