TMS27C040 524288 BY 8BIT UV ERASABLE

TMS27PC040 524288 BY 8BIT

PROGRAMMABLE READONLY MEMORY

SMLS040F − NOVEMBER 1990 − REVISED SEPTEMBER 1997

7

POST OFFICE BOX 1443

switching characteristics over recommended ranges of operating conditions (see Notes 3

and 4)

PARAMETER

TEST CONDITIONS

’27C040-10

’27 PC040-10

’27C040-12

’27 PC040-12

’27C040-15

’27 PC040-15

UNIT

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)

Access time from address

100

120

150

ns

ta(E)

Access time from chip enable

CL = 100 pF,

100

120

150

ns

ten(G) Output enable time from G

CL = 100 pF,

1 Series 74

TTL load,

50

50

50

ns

tdis

Output disable time from G or E, whichever

occurs first

1 Series 74

TTL load,

Input tr ≤ 20 ns,

Input tf ≤ 20 ns

0

50

0

50

0

50

ns

tv(A)

Output data valid time after change of

address, E, or G, whichever occurs first†

Input tf ≤ 20 ns

0

0

0

ns

† Value calculated from 0.5-V delta to measured output level.

NOTES:

3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low. (See Figure 2)

4. Common test conditions apply for tdis except during programming.

(see Note 3)

PARAMETER

MIN

MAX

UNIT

tdis(G)

Output disable time from G

0

100

ns

ten(G)

Output enable time from G

150

ns

NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low. (See Figure 2)

timing requirements for programming

MIN

NOM

MAX

UNIT

tw(PGM)

Pulse duration, program

SNAP! Pulse programming algorithm

95

100

105

µs

tsu(A)

Setup time, address

2

µs

tsu(E)

Setup time, E

2

µs

tsu(G)

Setup time, G

2

µs

tsu(D)

Setup time, data

2

µs

tsu(VPP)

Setup time, VPP

2

µs

tsu(VCC) Setup time, VCC

2

µs

th(A)

Hold time, address

0

µs

th(D)

Hold time, data

2

µs