FTLQ8181EBLM Product Specification – October 2014

 Finisar Corporation – 11-Oct-14 Rev. C2 Finisar Confidential

Page 5

III.

Parameter

Symbol

Min

Typ

Max

Unit

Ref.

Supply Voltage

Vcc

3.13

3.47

V

Supply Current

Icc

1.74

A

Module total power

P

6

W

1

Transmitter



Signaling rate per lane

10.3125

Gb/s

2

Input differential impedance

100



3

Differential data input swing per lane

Vin,pp

760

mV

4

Data input rise time tolerance

24

ps

5

Data input rise time tolerance

24

ps

5

Electrical input eye mask definition

{X1, X2}

{Y1, Y2}

{0.31, 0.5}

{42.5, 425}

UI

mV

Receiver



Signaling rate per lane

10.3125

Gb/s

2

Differential data output swing per lane

Vout,pp

760

mV

Data output rise time

24

ps

5

Data output fall time

24

ps

5

Electrical output eye mask definition

{X1, X2}

{Y1, Y2}

{0.2, 0.5}

{136, 380}

UI

mV

Power Supply Noise Tolerance

Vrip

See Note 5 below

6

Notes:

1.

Maximum total power value is specified across the full temperature and voltage range.

2.

+/- 100ppm

3.

After internal AC coupling.

4.

Host is expected to be compliant with IEEE 802.3ba, clause 83A.

5.

20% to 80%

6.

Per Table 4-1 in the CFP MSA Specification

FTLQ8181EBLM Clocking Signals

Clock

Name

Status

I/O

Value

REFCLK

Not Required

I

N/A

TX_MCLK

Not Supported

O

N/A

RX_MCLK

Not Supported

O

N/A