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RM48L930 Datasheet(PDF) 1 Page - Texas Instruments |
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RM48L930 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 172 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community RM48L930, RM48L730, RM48L530 SPNS176C – APRIL 2012 – REVISED JUNE 2015 RM48Lx30 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Microcontroller for Safety- • Multiple Communication Interfaces Critical Applications – USB – Dual CPUs Running in Lockstep • 2-Port USB Host Controller – ECC on Flash and RAM Interfaces • One Full-Speed USB Device Port – Built-In Self-Test (BIST) for CPU and On-chip – Three CAN Controllers (DCANs) RAMs • 64 Mailboxes, Each With Parity Protection – Error Signaling Module With Error Pin • Compliant to CAN Protocol Version 2.0B – Voltage and Clock Monitoring – Standard Serial Communication Interface (SCI) • ARM® Cortex®-R4F 32-Bit RISC CPU – Local Interconnect Network (LIN) Interface – Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline Controller – FPU With Single- and Double-Precision • Compliant to LIN Protocol Version 2.1 – 12-Region Memory Protection Unit (MPU) • Can be Configured as a Second SCI – Open Architecture With Third-Party Support – Inter-Integrated Circuit (I2C) • Operating Conditions – Three Multibuffered Serial Peripheral Interfaces – System Clock up to 200 MHz (MibSPIs) – Core Supply Voltage (VCC): 1.2 V Nominal • 128 Words With Parity Protection Each – I/O Supply Voltage (VCCIO): 3.3 V Nominal – Two Standard Serial Peripheral Interfaces (SPIs) – ADC Supply Voltage (VCCAD): 3.0 to 5.25 V • Two Next Generation High-End Timer (N2HET) • Integrated Memory Modules – 3MB of Program Flash With ECC (RM48L930) – N2HET1: 32 Programmable Channels – 2MB of Program Flash With ECC – N2HET2: 18 Programmable Channels (RM48L730/530) – 160-Word Instruction RAM Each With Parity – 256KB of RAM With ECC (RM48L930/730) Protection – 192KB of RAM With ECC (RM48L530) – Each N2HET Includes Hardware Angle – 64KB of Flash With ECC for Emulated Generator EEPROM – Dedicated High-End Transfer Unit (HTU) With • 16-Bit External Memory Interface MPU for Each N2HET • Common Platform Architecture • Two 12-Bit Multibuffered ADC Modules – Consistent Memory Map Across Family – ADC1: 24 Channels – Real-Time Interrupt (RTI) Timer OS Timer – ADC2: 16 Channels Shared With ADC1 – 96-Channel Vectored Interrupt Module (VIM) – 64 Result Buffers With Parity Protection Each – 2-Channel Cyclic Redundancy Checker (CRC) • General-Purpose Input/Output (GPIO) Pins • Direct Memory Access (DMA) Controller Capable of Generating Interrupts – 16 Channels and 32 Peripheral Requests – 16 Pins on the ZWT Package – Parity Protection for Control Packet RAM – 10 Pins on the PGE Package – DMA Accesses Protected by Dedicated MPU • IEEE 1149.1 JTAG, Boundary Scan and ARM • Frequency-Modulated Phase-Locked Loop CoreSight™ Components (FMPLL) With Built-In Slip Detector • JTAG Security Module • Separate Nonmodulating PLL • Packages • Trace and Calibration Capabilities – 144-Pin Quad Flatpack (PGE) [Green] – Embedded Trace Macrocell (ETM-R4) – 337-Ball Grid Array (ZWT) [Green] – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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