TMS45160, TMS45160P

262144WORD BY 16BIT HIGHSPEED

DYNAMIC RANDOMACCESS MEMORIES

SMHS160D − AUGUST 1992 − REVISED JUNE 1995

8

POST OFFICE BOX 655303

POST OFFICE BOX 1443

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature

PARAMETER

’45160 - 60

’45160P - 60

’45160 - 70

’45160P - 70

’45160 - 80

’45160P - 80

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tCAC

Access time from xCAS low

15

20

20

ns

tAA

Access time from column address

30

35

40

ns

tRAC

Access time from RAS low

60

70

80

ns

tOEA

Access time from OE low

15

20

20

ns

tCPA

Access time from column precharge

35

40

45

ns

tCLZ

Delay time, xCAS low to output in low impedance

0

0

0

ns

tOFF

Output disable time after xCAS high (see Note 4)

0

15

0

20

0

20

ns

tOEZ

Output disable time after OE high (see Note 4)

0

15

0

20

0

20

ns

NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Note 5)

’45160 - 60

’45160P - 60

’45160 - 70

’45160P - 70

’45160 - 80

’45160P - 80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tRC

Cycle time, read (see Note 6)

110

130

150

ns

tWC

Cycle time, write

110

130

150

ns

tRWC

Cycle time, read-write/read-modify-write

155

185

205

ns

tPC

Cycle time, page-mode read or write (see Note 7)

40

45

50

ns

tPRWC

Cycle time, page-mode read-modify-write

85

90

105

ns

tRASP

Pulse duration, RAS low, page mode (see Note 8)

60

100 000

70

100 000

80

100 000

ns

tRAS

Pulse duration, RAS low, nonpage mode (see Note 8)

60

10 000

70

10 000

80

10 000

ns

tCAS

Pulse duration, xCAS low (see Note 9)

15

10 000

20

10 000

20

10 000

ns

tCP

Pulse duration, xCAS high

10

10

10

ns

tRP

Pulse duration, RAS high (precharge)

40

50

60

ns

tWP

Pulse duration, write

15

15

15

ns

tASC

Setup time, column address before xCAS low

0

0

0

ns

tASR

Setup time, row address before RAS low

0

0

0

ns

tDS

Setup time, data before W low (see Note 10)

0

0

0

ns

tRCS

Setup time, read before xCAS low

0

0

0

ns

tCWL

Setup time, W low before xCAS high

15

20

20

ns

tRWL

Setup time, W low before RAS high

15

20

20

ns

tWCS

Setup time, W low before xCAS low (see Note 11)

0

0

0

ns

NOTES:

5. Timing measurements are referenced to VIL max and VIH min.

6. All cycle times assume tT = 5 ns.

7. To assure tPC min, tASC should be ≥ tCP .

8. In a read-modify-write cycle, tRWD and tRWL must be observed.

9. In a read-modify-write cycle, tCWD and tCWL must be observed.

10. Referenced to the later of xCAS or W in write operations

11. Early-write operation only