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TMS320F28PLC83PNT Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320F28PLC83PNT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 132 page  TMS320F28PLC84, TMS320F28PLC83 SPRS802 – SEPTEMBER 2014 www.ti.com Table 4-1. Signal Descriptions(1) (continued) TERMINAL I/O/Z DESCRIPTION PN NAME PIN NO. CLOCK See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of See XCLKOUT O/Z XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT GPIO18 = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to See GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a GPIO19 crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. XCLKIN I and NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal GPIO38 device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This action is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator X1 48 I must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected X2 47 O across X1 and X2. If X2 is not used, X2 must be left unconnected. RESET Device Reset (in) and Watchdog Reset (out). The F28PLC8x device has a built-in power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-out condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the device when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 k Ω and 10 kΩ should be placed between XRS and VDDIO. If a XRS 9 I/OD capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. ( ↑) 10 Terminal Configuration and Functions Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28PLC84 TMS320F28PLC83 |
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