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IDT72V243L15BC Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72V243L15BC Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 45 page 7 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 Symbol Name I/O Description PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES) NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 41-44 and Figures 31-33. PIN DESCRIPTION (BGA PACKAGE ONLY) Symbol Name I/O Description ASYR(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW WritePort will select Asynchronous operation. TCK(2) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data Input seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data Output seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode Select I TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND. RM(1) RetransmitTiming I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select Mode normal latency mode. RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. SEN Serial Enable I SENenablesserialloadingofprogrammableflagoffsets. WCLK/ WriteClock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK WR WriteStrobe writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, ( WENshouldbetiedtoitsactivestate).Asynchronousoperation of the WCLK/WR input is only available in the BGA package. WEN WriteEnable I WEN enables WCLK for writing data into the FIFO memory and offset registers. VCC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail. NOTE: 1. Inputs should not change state after Master Reset. |
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