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DS280BR820ZBLT Datasheet(PDF) 1 Page - Texas Instruments |
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DS280BR820ZBLT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page VDD RX7P RX7N ADDR0 ADDR1 SDC (1) READ_EN_N ALL_DONE_N SDA (1) TX7P TX7N . . . . . . GND . . . (1) SMBus signals need to be pulled up elsewhere in the system. . . . Float for SMBus Slave mode, or connect to next GHYLFH¶V 5($'_EN_N for SMBus Master mode VDD 1 F (2x) 0.1 F (4x) SMBus Slave mode SMBus Slave mode 2.5V . . . EN_SMB Address straps (pull-up, pull-down, or float) 1 NŸ To system SMBus RX0P RX0N TX0P TX0N Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS280BR820 SNLS537 – AUGUST 2016 DS280BR820 Low Power 28 Gbps 8 Channel Linear Repeater 1 1 Features 1 • Octal-Channel Multi-Protocol Linear Equalizer Supporting up to 28 Gbps Interfaces • Low Power Consumption: 93 mW / Channel (Typical) • No Heat Sink Required • Linear Equalization for Seamless Support of Link Training, Auto-Negotiation, and FEC Pass- Through • Extends Channel Reach by 17 dB+ Beyond Normal ASIC-to-ASIC Capability • Ultra-Low Latency: 100 ps (Typical) • Low Additive Random Jitter • Small 8-mm x 13-mm BGA Package with Integrated RX AC Coupling Capacitors for Easy Flow-Through Routing • Unique Pinout Allows Routing High-Speed Signals Underneath the Package • Pin-Compatible Retimer Available • Single 2.5-V ±5% Power Supply • –40°C to +85°C Operating Temperature Range 2 Applications • Backplane/Mid-Plane Reach Extension • Front-Port Eye Opener for Optical and Passive Copper (100G-SR4/LR4/CR4) • QSFP28, SFP28, CFP2, CFP4, CDFP 3 Description The DS280BR820 is an extremely low-power, high- performance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbps. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. The linear nature of the DS280BR820’s equalization preserves the transmit signal characteristics, thereby allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G- CR4/KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. Each channel operates independently, which allows the DS280BR820 to support individual lane Forward Error Correction (FEC) pass-through. The DS280BR820's small package dimensions, optimized high-speed signal escape, and the pin- compatible Retimer portfolio make the DS280BR820 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100G- SR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP2/CFP4, and CDFP without the need for a heat sink. Integrated AC coupling capacitors (RX side) eliminate the need for external capacitors on the PCB. The DS280BR820 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible Retimer device is available for longer reach applications. The DS280BR820 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) DS280BR820 nFBGA (135) 8.0 mm x 13.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic |
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