MSP430P325

MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

6

POST OFFICE BOX 655303

operation modes and interrupts (continued)

The most general bits that influence current consumption and support fast turnon from low-power operating

modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:

SCG1, SCG0, OscOff, and CPUOff.

Reserved For Future

Enhancements

15

9

8

7

0

V

SCG1

SCG0

OscOff

CPUOff

GIE

N

Z

C

rw-0

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range of

0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction

sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up, external reset, watchdog

WDTIFG (see Note1)

Reset

0FFFEh

15, highest

NMI, oscillator fault

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 4)

Non-maskable,

(Non)-maskable

0FFFCh

14

Dedicated I/O P0.0

P0.0IFG

Maskable

0FFFAh

13

Dedicated I/O P0.1 or 8-Bit Timer/Counter

RXD

P0.1IFG

Maskable

0FFF8h

12

0FFF6h

11

Watchdog Timer

WDTIFG

Maskable

0FFF4h

10

0FFF2h

9

0FFF0h

8

0FFEEh

7

0FFECh

6

ADC

ADCIFG

Maskable

0FFEAh

5

Timer/Port

RC1FG, RC2FG, EN1FG

(see Note 2)

Maskable

0FFE8h

4

0FFE6h

3

0FFE4h

2

Basic Timer1

BTIFG

Maskable

0FFE2h

1

I/O port 0, P0.2–7

P0.27IFG (see Note 1)

Maskable

0FFE0h

0, lowest

NOTES:

1. Multiple source flags

2. Timer/Port interrupt flags are located in the T/P registers

3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.