DS1746/DS1746P

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DS1746 BLOCK DIAGRAM Figure 1

PACKAGES

The DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP

style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin

PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)

that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the

DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery due to the high temperatures required for solder

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

CLOCK OPERATIONS-READING THE CLOCK

While the double buffered register structure reduces the chance of reading incorrect data, internal updates

to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As

long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the

count, that is day, date, and time that was current at the moment the halt command was issued. However,

the internal clock registers of the double buffered system continue to update so that the clock accuracy is

not affected by the access of data. All of the DS1746 registers are updated simultaneously after the

internal clock register updating process has been re-enabled. Updating is within a second after the read bit

is written to zero. The READ bit must be a zero for a minimum of 500

µs to ensure the external registers

will be updated.