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EQCO62T20.3 Datasheet(PDF) 9 Page - Microchip Technology |
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EQCO62T20.3 Datasheet(HTML) 9 Page - Microchip Technology |
9 / 32 page 2011-2016 Microchip Technology Inc. DS60001301B-page 9 EQCO62T20.3/EQCO31T20.3 2.1 Guidelines for PCB Layout When using the EQCO62T/R20 chipset at its full purpose, including low-speed uplink and power supply transmission, it is important not to disturb the RF- performance of the high-speed downlink channel. Implementing the circuit illustrated in Figure 2-1 with a different PCB layout will in first instance not deliver full data sheet performance. The simplest way of meeting optimal performance, including jitter and return-loss requirements, is to precisely follow the component and layout recommendations. Note that at multi-gigabit speeds, using "equivalent" components or small PCB layout changes (even moving a via) can have significant detrimental effects. The easiest way for achieving the requirements of the CoaXPress 1.1 specification is to use the recommended circuits, components and layout illustrated in Figure 2-1. For easy implementation, Microchip will provide the Gerber file. Please ask for it by email. 2.1.1 RIGHT ANGLE BNC Figure 2-2 below shows the four layers of the recommended footprint for the EQCO62T20.3 chip and the off-chip components that are critical for the RF-performance of the system. FIGURE 2-2: RECOMMENDED PCB LAYOUT FOR EQCO62T20.3 Note: Email address: coaxpress@microchip.com |
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