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EQCO30T5.2 Datasheet(PDF) 6 Page - Microchip Technology |
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EQCO30T5.2 Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 22 page  EQCO30T5.2 DS60001303C-page 6 2012-2016 Microchip Technology Inc. 1.1.4 SD/HDB With SD/HDB set to high, the output rise and fall times are set for SD operation. When left floating or pulled low, the rise and fall times are set for 3G/HD operation. 1.1.5 SDOn, SDOp The output driver is not based on a CML output stage. Both outputs operate independently, so there is very little interference between the outputs and their termination condition. There is also no LR- output network needed for achieving good return- loss. A 25Ω resistor should be connected in series with the output to drive a 75Ω coax cable. The output amplitude is achieved behind this 25Ω resistor; refer to the application circuits at the end of the data sheet. The PCB doesn’t require layout changes when migrating from competing cable drivers, however, fewer components are needed. One does not need to optimize the return-loss network, since it is omitted. 1.1.6 LFOUT LFout provides the 5 Mbps received uplink signal (LVTTL voltage levels). It can easily drive a PCB trace of 20 pF at this speed. For longer distance communication from this pin to the next chip, using a buffer is recommended. The output impedance is about 300Ω. 1.1.7 EQdis When EQdis is left floating or pulled low, the input trace equalization is turned on and invokes a typical 3 dB gain at 1.5 GHz. This value is optimized for compensating the high- frequency losses of approximately 20 cm of 5-mil stripline in FR4. When pulled high, this equalization is turned off. |
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