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A29160BUG-55UF Datasheet(PDF) 3 Page - AMIC Technology |
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A29160BUG-55UF Datasheet(HTML) 3 Page - AMIC Technology |
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3 / 43 page  A29160B Series PRELIMINARY (June, 2016, Version 0.0) 2 AMIC Technology, Corp. algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29160B is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Write Protect ( WP ) features protects the 16 Kbyte boot sector from erasure by asserting a logic low on the WP pin, whether or not the sector had been previously protected. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers power-saving features. The system can place the device into the standby mode. Power consumption is greatly reduced in the standby modes. Pin Configurations TSOP (I) A29160BV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A14 A13 A12 A11 A10 A9 A8 NC WE RESET NC WP RY/BY A18 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 I/O2 I/O10 I/O13 I/O11 VCC I/O4 I/O12 I/O5 I/O13 I/O6 I/O14 I/O7 I/O15(A-1) VSS BYTE A16 A15 A19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O9 I/O1 I/O8 I/O0 OE VSS CE A0 A17 A7 A6 A5 A4 A3 A2 A1 |
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