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S4MF03107SPZQQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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S4MF03107SPZQQ1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 68 page  TMS470MF04207 TMS470MF03107 www.ti.com SPNS159C – JANUARY 2012 2.1.2 Memory Selects Memories in the TMS470M devices are located at fixed addresses. Table 2-2 through Table 2-7 detail the mapping of the memory regions. Table 2-2. TMS470MF04207-Specific Memory Frame Assignment MEMORY FRAME NAME START ADDRESS ENDING ADDRESS MEMORY TYPE ACTUAL MEMORY 0x0000 0000 0x0005 FFFF Flash 384K Bytes nCS0(1) 0x0008 0000 0x0008 FFFF Flash 64K Bytes RAM-CLR 0x0810 0000 0x0810 5FFF Internal RAM 24K Bytes RAM-SET 0x0808 0000 0x0808 5FFF Internal RAM 24K Bytes 0x0800 0000 0x0800 5FFF Internal RAM 24K Bytes CSRAM0(1) 0x0840 0000 0x0840 5FFF Internal RAM-ECC 24K Bytes (1) Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. TI recommends the use of the MPU for protecting access to addresses outside the intended range of use. Table 2-3. TMS470MF03107-Specific Memory Frame Assignment MEMORY FRAME NAME START ADDRESS ENDING ADDRESS MEMORY TYPE ACTUAL MEMORY 0x0000 0000 0x0003 FFFF Flash 256K Bytes nCS0(1) 0x0008 0000 0x0008 FFFF Flash 64K Bytes RAM-CLR 0x0810 0000 0x0810 3FFF Internal RAM 16K Bytes RAM-SET 0x0808 0000 0x0808 3FFF Internal RAM 16K Bytes 0x0800 0000 0x0800 3FFF Internal RAM 16K Bytes CSRAM0(1) 0x0840 0000 0x0840 3FFF Internal RAM-ECC 16K Bytes (1) Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. TI recommends the use of the MPU for protecting access to addresses outside the intended range of use. Table 2-4. Memory Initialization and MBIST ADDRESS RANGE MEMORY INITIALIZATION MBIST CONTROLLER CONNECTING MODULE CHANNEL ENABLE CHANNEL BASE ADDRESS ENDING ADDRESS System RAM (TMS470MF04207) 0x0800 0000 0x0800 5FFF 0 0 System RAM (TMS470MF03107) 0x0800 0000 0x0800 3FFF 0 0 MibSPI1 RAM 0xFF0E 0000 0xFF0F FFFF 1 1 or 2(1) MibSPI2 RAM 0xFF0C 0000 0xFF0D FFFF 2 DCAN1 RAM 0xFF1E 0000 0xFF1F FFFF 3 3 or 4(1) DCAN2 RAM 0xFF1C 0000 0xFF1D FFFF 4 ADC RAM 0xFF3E 0000 0xFF3F FFFF 5 5 HET RAM 0xFF46 0000 0xFF47 FFFF Not Available 6 STC ROM Not Applicable Not Applicable Not Applicable 7 (1) There are single MBIST controllers for both MibSPI RAMs and both DCAN RAMs. The MBIST controller for both MibSPI RAMs is mapped to channels 1 and 2 and the MBIST controller for both DCAN RAMs is mapped to channels 3 and 4. MBIST on these modules can be initiated by selecting one of the 2 channels or both. Table 2-5. Peripheral Memory Chip Select Assignment ADDRESS RANGE PERIPHERAL CONNECTING MODULE SELECTS BASE ADDRESS ENDING ADDRESS MibSPI1 RAM 0xFF0E 0000 0xFF0F FFFF PCS[7] MibSPI2 RAM 0xFF0C 0000 0xFF0D FFFF PCS[6] DCAN1 RAM 0xFF1E 0000 0xFF1F FFFF PCS[14] DCAN2 RAM 0xFF1C 0000 0xFF1D FFFF PCS[15] Copyright © 2012, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Link(s): TMS470MF04207 TMS470MF03107 |
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